templog: server/ts.py annotate

annotate server/ts.py @ 405:d9b78a1bdd1d

fix off-by-one in remainder code

author	Matt Johnston <matt@ucc.asn.au>
date	Tue, 17 Jul 2012 21:58:49 +0800
parents	1137f315209b
children	9485da05bc11

rev	line source
327 5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	1 #!/usr/bin/env python2.7
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	2
329 740438e21ea0 Fix bugs in server code (try actually running it) Matt Johnston <matt@ucc.asn.au> parents: 328 diff changeset	3 # time that the bluetooth takes to get going?
740438e21ea0 Fix bugs in server code (try actually running it) Matt Johnston <matt@ucc.asn.au> parents: 328 diff changeset	4 EXTRA_WAKEUP = 0
740438e21ea0 Fix bugs in server code (try actually running it) Matt Johnston <matt@ucc.asn.au> parents: 328 diff changeset	5
330 7ac6b8846eea - some fixes for server code Matt Johnston <matt@ucc.asn.au> parents: 329 diff changeset	6 FETCH_TRIES = 3
7ac6b8846eea - some fixes for server code Matt Johnston <matt@ucc.asn.au> parents: 329 diff changeset	7
329 740438e21ea0 Fix bugs in server code (try actually running it) Matt Johnston <matt@ucc.asn.au> parents: 328 diff changeset	8 # avoid turning off the bluetooth etc.
348 536128b90573 mostly works Matt Johnston <matt@ucc.asn.au> parents: 346 diff changeset	9 TESTING = False
328 46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	10
327 5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	11 import sys
333 298e502fdcd4 Add some web server handling Matt Johnston <matt@ucc.asn.au> parents: 332 diff changeset	12 # for wrt
298e502fdcd4 Add some web server handling Matt Johnston <matt@ucc.asn.au> parents: 332 diff changeset	13 sys.path.append('/root/python')
298e502fdcd4 Add some web server handling Matt Johnston <matt@ucc.asn.au> parents: 332 diff changeset	14 import httplib
328 46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	15 import time
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	16 import traceback
334 3b821541657d hmac Matt Johnston <matt@ucc.asn.au> parents: 333 diff changeset	17 import binascii
3b821541657d hmac Matt Johnston <matt@ucc.asn.au> parents: 333 diff changeset	18 import hmac
340 3baca8d980f4 - import zlib Matt Johnston <matt@ucc.asn.au> parents: 338 diff changeset	19 import zlib
342 ba9bfcc9c526 - fix mac/urllib to work Matt Johnston <matt@ucc.asn.au> parents: 340 diff changeset	20 import urllib
ba9bfcc9c526 - fix mac/urllib to work Matt Johnston <matt@ucc.asn.au> parents: 340 diff changeset	21 import urllib2
395 f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	22 import logging
f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	23
f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	24 L = logging.info
f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	25 W = logging.warning
f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	26 E = logging.error
334 3b821541657d hmac Matt Johnston <matt@ucc.asn.au> parents: 333 diff changeset	27
3b821541657d hmac Matt Johnston <matt@ucc.asn.au> parents: 333 diff changeset	28 import config
328 46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	29
332 05c1249da994 - Move crc16 to utils and fix it Matt Johnston <matt@ucc.asn.au> parents: 331 diff changeset	30 from utils import monotonic_time, retry, readline, crc16
372 dae8eb26eaa3 dup2 to devnull Matt Johnston <matt@ucc.asn.au> parents: 371 diff changeset	31 import utils
327 5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	32
395 f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	33 import bluetooth
327 5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	34
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	35 def get_socket(addr):
395 f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	36 s = bluetooth.BluetoothSocket( bluetooth.RFCOMM )
f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	37 s.connect((addr, 1))
397 f1428cddb882 handle new next_wake format Matt Johnston <matt@ucc.asn.au> parents: 395 diff changeset	38 s.setblocking(False)
f1428cddb882 handle new next_wake format Matt Johnston <matt@ucc.asn.au> parents: 395 diff changeset	39
327 5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	40 return s
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	41
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	42
328 46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	43 @retry()
327 5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	44 def fetch(sock):
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	45 sock.send("fetch\n")
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	46
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	47 crc = 0
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	48
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	49 lines = []
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	50 l = readline(sock)
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	51 if l != 'START\n':
395 f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	52 W("Bad expected START line '%s'\n" % l.rstrip('\n'))
327 5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	53 return None
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	54 crc = crc16(l, crc)
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	55
330 7ac6b8846eea - some fixes for server code Matt Johnston <matt@ucc.asn.au> parents: 329 diff changeset	56 while True:
327 5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	57 l = readline(sock)
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	58
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	59 crc = crc16(l, crc)
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	60
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	61 if l == 'END\n':
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	62 break
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	63
333 298e502fdcd4 Add some web server handling Matt Johnston <matt@ucc.asn.au> parents: 332 diff changeset	64 lines.append(l.rstrip('\n'))
327 5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	65
395 f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	66 for d in lines:
f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	67 L("Received: %s" % d)
f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	68
327 5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	69 l = readline(sock)
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	70 recv_crc = None
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	71 try:
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	72 k, v = l.rstrip('\n').split('=')
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	73 if k == 'CRC':
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	74 recv_crc = int(v)
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	75 if recv_crc < 0 or recv_crc > 0xffff:
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	76 recv_crc = None
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	77 except ValueError:
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	78 pass
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	79
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	80 if recv_crc is None:
395 f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	81 W("Bad expected CRC line '%s'\n" % l.rstrip('\n'))
327 5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	82 return None
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	83
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	84 if recv_crc != crc:
395 f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	85 W("Bad CRC: calculated 0x%x vs received 0x%x\n" % (crc, recv_crc))
327 5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	86 return None
5639c74f2cbb untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	87
333 298e502fdcd4 Add some web server handling Matt Johnston <matt@ucc.asn.au> parents: 332 diff changeset	88 return lines
328 46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	89
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	90 @retry()
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	91 def turn_off(sock):
329 740438e21ea0 Fix bugs in server code (try actually running it) Matt Johnston <matt@ucc.asn.au> parents: 328 diff changeset	92 if TESTING:
348 536128b90573 mostly works Matt Johnston <matt@ucc.asn.au> parents: 346 diff changeset	93 return 99
395 f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	94 L("Sending btoff")
328 46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	95 sock.send("btoff\n");
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	96 # read newline
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	97 l = readline(sock)
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	98 if not l:
395 f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	99 W("Bad response to btoff")
328 46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	100 return None
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	101
397 f1428cddb882 handle new next_wake format Matt Johnston <matt@ucc.asn.au> parents: 395 diff changeset	102 if not l.startswith('next_wake'):
395 f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	103 W("Bad response to btoff '%s'" % l)
348 536128b90573 mostly works Matt Johnston <matt@ucc.asn.au> parents: 346 diff changeset	104 return None
397 f1428cddb882 handle new next_wake format Matt Johnston <matt@ucc.asn.au> parents: 395 diff changeset	105 L("Next wake line %s" % l)
328 46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	106
397 f1428cddb882 handle new next_wake format Matt Johnston <matt@ucc.asn.au> parents: 395 diff changeset	107 toks = dict(v.split('=') for v in l.split(','))
f1428cddb882 handle new next_wake format Matt Johnston <matt@ucc.asn.au> parents: 395 diff changeset	108
398 c738a52e31e4 handle rem from btoff Matt Johnston <matt@ucc.asn.au> parents: 397 diff changeset	109 rem = int(toks['rem'])
c738a52e31e4 handle rem from btoff Matt Johnston <matt@ucc.asn.au> parents: 397 diff changeset	110 tick_secs = int(toks['tick_secs'])
405 d9b78a1bdd1d fix off-by-one in remainder code Matt Johnston <matt@ucc.asn.au> parents: 400 diff changeset	111 tick_wake = int(toks['tick_wake']) + 1
398 c738a52e31e4 handle rem from btoff Matt Johnston <matt@ucc.asn.au> parents: 397 diff changeset	112 next_wake = int(toks['next_wake'])
c738a52e31e4 handle rem from btoff Matt Johnston <matt@ucc.asn.au> parents: 397 diff changeset	113
c738a52e31e4 handle rem from btoff Matt Johnston <matt@ucc.asn.au> parents: 397 diff changeset	114 rem_secs = float(rem) / tick_wake * tick_secs
c738a52e31e4 handle rem from btoff Matt Johnston <matt@ucc.asn.au> parents: 397 diff changeset	115
c738a52e31e4 handle rem from btoff Matt Johnston <matt@ucc.asn.au> parents: 397 diff changeset	116 next_wake_secs = next_wake - rem_secs
c738a52e31e4 handle rem from btoff Matt Johnston <matt@ucc.asn.au> parents: 397 diff changeset	117 L("next_wake_secs %f\n", next_wake_secs)
c738a52e31e4 handle rem from btoff Matt Johnston <matt@ucc.asn.au> parents: 397 diff changeset	118 return next_wake_secs
328 46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	119
338 12123e390169 More minor work Matt Johnston <matt@ucc.asn.au> parents: 335 diff changeset	120 @retry()
12123e390169 More minor work Matt Johnston <matt@ucc.asn.au> parents: 335 diff changeset	121 def clear_meas(sock):
12123e390169 More minor work Matt Johnston <matt@ucc.asn.au> parents: 335 diff changeset	122 sock.send("clear\n");
12123e390169 More minor work Matt Johnston <matt@ucc.asn.au> parents: 335 diff changeset	123 l = readline(sock)
12123e390169 More minor work Matt Johnston <matt@ucc.asn.au> parents: 335 diff changeset	124 if l and l.rstrip() == 'cleared':
12123e390169 More minor work Matt Johnston <matt@ucc.asn.au> parents: 335 diff changeset	125 return True
12123e390169 More minor work Matt Johnston <matt@ucc.asn.au> parents: 335 diff changeset	126
395 f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	127 E("Bad response to clear '%s'" % str(l))
338 12123e390169 More minor work Matt Johnston <matt@ucc.asn.au> parents: 335 diff changeset	128 return False
12123e390169 More minor work Matt Johnston <matt@ucc.asn.au> parents: 335 diff changeset	129
334 3b821541657d hmac Matt Johnston <matt@ucc.asn.au> parents: 333 diff changeset	130 def send_results(lines):
335 1e22eaf93620 work on web interface Matt Johnston <matt@ucc.asn.au> parents: 334 diff changeset	131 enc_lines = binascii.b2a_base64(zlib.compress('\n'.join(lines)))
342 ba9bfcc9c526 - fix mac/urllib to work Matt Johnston <matt@ucc.asn.au> parents: 340 diff changeset	132 mac = hmac.new(config.HMAC_KEY, enc_lines).hexdigest()
334 3b821541657d hmac Matt Johnston <matt@ucc.asn.au> parents: 333 diff changeset	133
342 ba9bfcc9c526 - fix mac/urllib to work Matt Johnston <matt@ucc.asn.au> parents: 340 diff changeset	134 url_data = urllib.urlencode( {'lines': enc_lines, 'hmac': mac} )
334 3b821541657d hmac Matt Johnston <matt@ucc.asn.au> parents: 333 diff changeset	135 con = urllib2.urlopen(config.UPDATE_URL, url_data)
338 12123e390169 More minor work Matt Johnston <matt@ucc.asn.au> parents: 335 diff changeset	136 result = con.read(100)
12123e390169 More minor work Matt Johnston <matt@ucc.asn.au> parents: 335 diff changeset	137 if result == 'OK':
12123e390169 More minor work Matt Johnston <matt@ucc.asn.au> parents: 335 diff changeset	138 return True
12123e390169 More minor work Matt Johnston <matt@ucc.asn.au> parents: 335 diff changeset	139 else:
395 f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	140 W("Bad result '%s'" % result)
338 12123e390169 More minor work Matt Johnston <matt@ucc.asn.au> parents: 335 diff changeset	141 return False
334 3b821541657d hmac Matt Johnston <matt@ucc.asn.au> parents: 333 diff changeset	142
328 46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	143 def do_comms(sock):
395 f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	144 L("do_comms")
328 46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	145 d = None
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	146 # serial could be unreliable, try a few times
395 f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	147 d = fetch(sock)
328 46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	148 if not d:
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	149 return
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	150
333 298e502fdcd4 Add some web server handling Matt Johnston <matt@ucc.asn.au> parents: 332 diff changeset	151 res = send_results(d)
328 46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	152 if not res:
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	153 return
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	154
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	155 clear_meas(sock)
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	156
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	157 next_wake = turn_off(sock)
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	158 sock.close()
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	159 return next_wake
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	160
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	161 testcount = 0
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	162
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	163 def sleep_for(secs):
329 740438e21ea0 Fix bugs in server code (try actually running it) Matt Johnston <matt@ucc.asn.au> parents: 328 diff changeset	164 until = monotonic_time() + secs
328 46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	165 while True:
330 7ac6b8846eea - some fixes for server code Matt Johnston <matt@ucc.asn.au> parents: 329 diff changeset	166 length = until - monotonic_time()
328 46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	167 if length <= 0:
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	168 return
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	169 time.sleep(length)
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	170
395 f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	171 def setup_logging():
f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	172 logging.basicConfig(format='%(asctime)s %(message)s',
397 f1428cddb882 handle new next_wake format Matt Johnston <matt@ucc.asn.au> parents: 395 diff changeset	173 datefmt='%m/%d/%Y %I:%M:%S %p',
f1428cddb882 handle new next_wake format Matt Johnston <matt@ucc.asn.au> parents: 395 diff changeset	174 level=logging.INFO)
395 f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	175
328 46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	176 def main():
395 f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	177 setup_logging()
f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	178
f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	179 L("Running templog rfcomm server")
328 46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	180
371 7dec59b7eeef cheap_daemon() Matt Johnston <matt@ucc.asn.au> parents: 353 diff changeset	181 if '--daemon' in sys.argv:
7dec59b7eeef cheap_daemon() Matt Johnston <matt@ucc.asn.au> parents: 353 diff changeset	182 utils.cheap_daemon()
7dec59b7eeef cheap_daemon() Matt Johnston <matt@ucc.asn.au> parents: 353 diff changeset	183
328 46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	184 while True:
329 740438e21ea0 Fix bugs in server code (try actually running it) Matt Johnston <matt@ucc.asn.au> parents: 328 diff changeset	185 sock = None
740438e21ea0 Fix bugs in server code (try actually running it) Matt Johnston <matt@ucc.asn.au> parents: 328 diff changeset	186 try:
388 b33045e7e08e move server config into config.py Matt Johnston <matt@ucc.asn.au> parents: 372 diff changeset	187 sock = get_socket(config.BTADDR)
329 740438e21ea0 Fix bugs in server code (try actually running it) Matt Johnston <matt@ucc.asn.au> parents: 328 diff changeset	188 except Exception, e:
400 1137f315209b use the remainder of times Matt Johnston <matt@ucc.asn.au> parents: 398 diff changeset	189 #logging.exception("Error connecting")
395 f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	190 pass
f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	191 next_wake_time = 0
328 46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	192 if sock:
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	193 try:
395 f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	194 avr_wake = do_comms(sock)
f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	195 next_wake_time = time.time() + avr_wake
328 46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	196 except Exception, e:
395 f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	197 logging.exception("Error in do_comms")
328 46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	198
395 f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	199 next_wake_interval = next_wake_time - time.time() - EXTRA_WAKEUP
f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	200 sleep_time = config.SLEEP_TIME
f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	201 if next_wake_interval > 0:
f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	202 sleep_time = min(next_wake_interval, sleep_time)
f0ddb75bcf04 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 388 diff changeset	203 L("Sleeping for %d, next wake time %f" % (sleep_time, next_wake_time))
328 46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	204 sleep_for(sleep_time)
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	205
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	206 if __name__ == '__main__':
46070aaf29ea A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 327 diff changeset	207 main()

Mercurial > templog

annotate server/ts.py @ 405:d9b78a1bdd1d