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1 //#include "arm_arch.h" |
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2 #define __ARM_ARCH__ 6 |
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3 |
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4 .text |
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5 |
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6 .global sha1_block_data_order |
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7 .type sha1_block_data_order,%function |
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8 |
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9 .align 2 |
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10 sha1_block_data_order: |
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11 stmdb sp!,{r4-r12,lr} |
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12 add r2,r1,r2,lsl#6 @ r2 to point at the end of r1 |
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13 ldmia r0,{r3,r4,r5,r6,r7} |
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14 .Lloop: |
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15 ldr r8,.LK_00_19 |
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16 mov r14,sp |
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17 sub sp,sp,#15*4 |
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18 mov r5,r5,ror#30 |
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19 mov r6,r6,ror#30 |
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20 mov r7,r7,ror#30 @ [6] |
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21 .L_00_15: |
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22 #if __ARM_ARCH__<7 |
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23 ldrb r10,[r1,#2] |
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24 ldrb r9,[r1,#3] |
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25 ldrb r11,[r1,#1] |
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26 add r7,r8,r7,ror#2 @ E+=K_00_19 |
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27 ldrb r12,[r1],#4 |
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28 orr r9,r9,r10,lsl#8 |
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29 eor r10,r5,r6 @ F_xx_xx |
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30 orr r9,r9,r11,lsl#16 |
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31 add r7,r7,r3,ror#27 @ E+=ROR(A,27) |
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32 orr r9,r9,r12,lsl#24 |
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33 #else |
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34 ldr r9,[r1],#4 @ handles unaligned |
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35 add r7,r8,r7,ror#2 @ E+=K_00_19 |
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36 eor r10,r5,r6 @ F_xx_xx |
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37 add r7,r7,r3,ror#27 @ E+=ROR(A,27) |
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38 #ifdef __ARMEL__ |
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39 rev r9,r9 @ byte swap |
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40 #endif |
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41 #endif |
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42 and r10,r4,r10,ror#2 |
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43 add r7,r7,r9 @ E+=X[i] |
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44 eor r10,r10,r6,ror#2 @ F_00_19(B,C,D) |
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45 str r9,[r14,#-4]! |
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46 add r7,r7,r10 @ E+=F_00_19(B,C,D) |
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47 #if __ARM_ARCH__<7 |
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48 ldrb r10,[r1,#2] |
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49 ldrb r9,[r1,#3] |
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50 ldrb r11,[r1,#1] |
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51 add r6,r8,r6,ror#2 @ E+=K_00_19 |
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52 ldrb r12,[r1],#4 |
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53 orr r9,r9,r10,lsl#8 |
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54 eor r10,r4,r5 @ F_xx_xx |
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55 orr r9,r9,r11,lsl#16 |
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56 add r6,r6,r7,ror#27 @ E+=ROR(A,27) |
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57 orr r9,r9,r12,lsl#24 |
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58 #else |
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59 ldr r9,[r1],#4 @ handles unaligned |
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60 add r6,r8,r6,ror#2 @ E+=K_00_19 |
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61 eor r10,r4,r5 @ F_xx_xx |
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62 add r6,r6,r7,ror#27 @ E+=ROR(A,27) |
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63 #ifdef __ARMEL__ |
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64 rev r9,r9 @ byte swap |
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65 #endif |
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66 #endif |
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67 and r10,r3,r10,ror#2 |
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68 add r6,r6,r9 @ E+=X[i] |
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69 eor r10,r10,r5,ror#2 @ F_00_19(B,C,D) |
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70 str r9,[r14,#-4]! |
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71 add r6,r6,r10 @ E+=F_00_19(B,C,D) |
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72 #if __ARM_ARCH__<7 |
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73 ldrb r10,[r1,#2] |
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74 ldrb r9,[r1,#3] |
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75 ldrb r11,[r1,#1] |
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76 add r5,r8,r5,ror#2 @ E+=K_00_19 |
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77 ldrb r12,[r1],#4 |
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78 orr r9,r9,r10,lsl#8 |
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79 eor r10,r3,r4 @ F_xx_xx |
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80 orr r9,r9,r11,lsl#16 |
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81 add r5,r5,r6,ror#27 @ E+=ROR(A,27) |
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82 orr r9,r9,r12,lsl#24 |
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83 #else |
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84 ldr r9,[r1],#4 @ handles unaligned |
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85 add r5,r8,r5,ror#2 @ E+=K_00_19 |
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86 eor r10,r3,r4 @ F_xx_xx |
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87 add r5,r5,r6,ror#27 @ E+=ROR(A,27) |
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88 #ifdef __ARMEL__ |
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89 rev r9,r9 @ byte swap |
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90 #endif |
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91 #endif |
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92 and r10,r7,r10,ror#2 |
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93 add r5,r5,r9 @ E+=X[i] |
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94 eor r10,r10,r4,ror#2 @ F_00_19(B,C,D) |
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95 str r9,[r14,#-4]! |
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96 add r5,r5,r10 @ E+=F_00_19(B,C,D) |
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97 #if __ARM_ARCH__<7 |
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98 ldrb r10,[r1,#2] |
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99 ldrb r9,[r1,#3] |
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100 ldrb r11,[r1,#1] |
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101 add r4,r8,r4,ror#2 @ E+=K_00_19 |
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102 ldrb r12,[r1],#4 |
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103 orr r9,r9,r10,lsl#8 |
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104 eor r10,r7,r3 @ F_xx_xx |
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105 orr r9,r9,r11,lsl#16 |
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106 add r4,r4,r5,ror#27 @ E+=ROR(A,27) |
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107 orr r9,r9,r12,lsl#24 |
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108 #else |
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109 ldr r9,[r1],#4 @ handles unaligned |
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110 add r4,r8,r4,ror#2 @ E+=K_00_19 |
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111 eor r10,r7,r3 @ F_xx_xx |
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112 add r4,r4,r5,ror#27 @ E+=ROR(A,27) |
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113 #ifdef __ARMEL__ |
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114 rev r9,r9 @ byte swap |
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115 #endif |
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116 #endif |
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117 and r10,r6,r10,ror#2 |
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118 add r4,r4,r9 @ E+=X[i] |
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119 eor r10,r10,r3,ror#2 @ F_00_19(B,C,D) |
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120 str r9,[r14,#-4]! |
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121 add r4,r4,r10 @ E+=F_00_19(B,C,D) |
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122 #if __ARM_ARCH__<7 |
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123 ldrb r10,[r1,#2] |
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124 ldrb r9,[r1,#3] |
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125 ldrb r11,[r1,#1] |
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126 add r3,r8,r3,ror#2 @ E+=K_00_19 |
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127 ldrb r12,[r1],#4 |
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128 orr r9,r9,r10,lsl#8 |
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129 eor r10,r6,r7 @ F_xx_xx |
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130 orr r9,r9,r11,lsl#16 |
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131 add r3,r3,r4,ror#27 @ E+=ROR(A,27) |
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132 orr r9,r9,r12,lsl#24 |
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133 #else |
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134 ldr r9,[r1],#4 @ handles unaligned |
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135 add r3,r8,r3,ror#2 @ E+=K_00_19 |
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136 eor r10,r6,r7 @ F_xx_xx |
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137 add r3,r3,r4,ror#27 @ E+=ROR(A,27) |
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138 #ifdef __ARMEL__ |
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139 rev r9,r9 @ byte swap |
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140 #endif |
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141 #endif |
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142 and r10,r5,r10,ror#2 |
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143 add r3,r3,r9 @ E+=X[i] |
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144 eor r10,r10,r7,ror#2 @ F_00_19(B,C,D) |
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145 str r9,[r14,#-4]! |
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146 add r3,r3,r10 @ E+=F_00_19(B,C,D) |
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147 teq r14,sp |
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148 bne .L_00_15 @ [((11+4)*5+2)*3] |
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149 sub sp,sp,#25*4 |
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150 #if __ARM_ARCH__<7 |
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151 ldrb r10,[r1,#2] |
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152 ldrb r9,[r1,#3] |
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153 ldrb r11,[r1,#1] |
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154 add r7,r8,r7,ror#2 @ E+=K_00_19 |
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155 ldrb r12,[r1],#4 |
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156 orr r9,r9,r10,lsl#8 |
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157 eor r10,r5,r6 @ F_xx_xx |
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158 orr r9,r9,r11,lsl#16 |
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159 add r7,r7,r3,ror#27 @ E+=ROR(A,27) |
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160 orr r9,r9,r12,lsl#24 |
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161 #else |
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162 ldr r9,[r1],#4 @ handles unaligned |
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163 add r7,r8,r7,ror#2 @ E+=K_00_19 |
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164 eor r10,r5,r6 @ F_xx_xx |
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165 add r7,r7,r3,ror#27 @ E+=ROR(A,27) |
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166 #ifdef __ARMEL__ |
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167 rev r9,r9 @ byte swap |
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168 #endif |
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169 #endif |
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170 and r10,r4,r10,ror#2 |
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171 add r7,r7,r9 @ E+=X[i] |
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172 eor r10,r10,r6,ror#2 @ F_00_19(B,C,D) |
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173 str r9,[r14,#-4]! |
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174 add r7,r7,r10 @ E+=F_00_19(B,C,D) |
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175 ldr r9,[r14,#15*4] |
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176 ldr r10,[r14,#13*4] |
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177 ldr r11,[r14,#7*4] |
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178 add r6,r8,r6,ror#2 @ E+=K_xx_xx |
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179 ldr r12,[r14,#2*4] |
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180 eor r9,r9,r10 |
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181 eor r11,r11,r12 @ 1 cycle stall |
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182 eor r10,r4,r5 @ F_xx_xx |
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183 mov r9,r9,ror#31 |
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184 add r6,r6,r7,ror#27 @ E+=ROR(A,27) |
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185 eor r9,r9,r11,ror#31 |
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186 str r9,[r14,#-4]! |
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187 and r10,r3,r10,ror#2 @ F_xx_xx |
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188 @ F_xx_xx |
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189 add r6,r6,r9 @ E+=X[i] |
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190 eor r10,r10,r5,ror#2 @ F_00_19(B,C,D) |
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191 add r6,r6,r10 @ E+=F_00_19(B,C,D) |
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192 ldr r9,[r14,#15*4] |
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193 ldr r10,[r14,#13*4] |
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194 ldr r11,[r14,#7*4] |
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195 add r5,r8,r5,ror#2 @ E+=K_xx_xx |
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196 ldr r12,[r14,#2*4] |
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197 eor r9,r9,r10 |
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198 eor r11,r11,r12 @ 1 cycle stall |
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199 eor r10,r3,r4 @ F_xx_xx |
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200 mov r9,r9,ror#31 |
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201 add r5,r5,r6,ror#27 @ E+=ROR(A,27) |
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202 eor r9,r9,r11,ror#31 |
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203 str r9,[r14,#-4]! |
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204 and r10,r7,r10,ror#2 @ F_xx_xx |
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205 @ F_xx_xx |
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206 add r5,r5,r9 @ E+=X[i] |
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207 eor r10,r10,r4,ror#2 @ F_00_19(B,C,D) |
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208 add r5,r5,r10 @ E+=F_00_19(B,C,D) |
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209 ldr r9,[r14,#15*4] |
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210 ldr r10,[r14,#13*4] |
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211 ldr r11,[r14,#7*4] |
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212 add r4,r8,r4,ror#2 @ E+=K_xx_xx |
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213 ldr r12,[r14,#2*4] |
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214 eor r9,r9,r10 |
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215 eor r11,r11,r12 @ 1 cycle stall |
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216 eor r10,r7,r3 @ F_xx_xx |
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217 mov r9,r9,ror#31 |
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218 add r4,r4,r5,ror#27 @ E+=ROR(A,27) |
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219 eor r9,r9,r11,ror#31 |
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220 str r9,[r14,#-4]! |
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221 and r10,r6,r10,ror#2 @ F_xx_xx |
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222 @ F_xx_xx |
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223 add r4,r4,r9 @ E+=X[i] |
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224 eor r10,r10,r3,ror#2 @ F_00_19(B,C,D) |
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225 add r4,r4,r10 @ E+=F_00_19(B,C,D) |
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226 ldr r9,[r14,#15*4] |
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227 ldr r10,[r14,#13*4] |
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228 ldr r11,[r14,#7*4] |
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229 add r3,r8,r3,ror#2 @ E+=K_xx_xx |
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230 ldr r12,[r14,#2*4] |
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231 eor r9,r9,r10 |
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232 eor r11,r11,r12 @ 1 cycle stall |
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233 eor r10,r6,r7 @ F_xx_xx |
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234 mov r9,r9,ror#31 |
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235 add r3,r3,r4,ror#27 @ E+=ROR(A,27) |
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236 eor r9,r9,r11,ror#31 |
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237 str r9,[r14,#-4]! |
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238 and r10,r5,r10,ror#2 @ F_xx_xx |
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239 @ F_xx_xx |
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240 add r3,r3,r9 @ E+=X[i] |
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241 eor r10,r10,r7,ror#2 @ F_00_19(B,C,D) |
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242 add r3,r3,r10 @ E+=F_00_19(B,C,D) |
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243 |
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244 ldr r8,.LK_20_39 @ [+15+16*4] |
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245 cmn sp,#0 @ [+3], clear carry to denote 20_39 |
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246 .L_20_39_or_60_79: |
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247 ldr r9,[r14,#15*4] |
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248 ldr r10,[r14,#13*4] |
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249 ldr r11,[r14,#7*4] |
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250 add r7,r8,r7,ror#2 @ E+=K_xx_xx |
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251 ldr r12,[r14,#2*4] |
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252 eor r9,r9,r10 |
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253 eor r11,r11,r12 @ 1 cycle stall |
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254 eor r10,r5,r6 @ F_xx_xx |
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255 mov r9,r9,ror#31 |
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256 add r7,r7,r3,ror#27 @ E+=ROR(A,27) |
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257 eor r9,r9,r11,ror#31 |
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258 str r9,[r14,#-4]! |
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259 eor r10,r4,r10,ror#2 @ F_xx_xx |
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260 @ F_xx_xx |
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261 add r7,r7,r9 @ E+=X[i] |
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262 add r7,r7,r10 @ E+=F_20_39(B,C,D) |
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263 ldr r9,[r14,#15*4] |
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264 ldr r10,[r14,#13*4] |
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265 ldr r11,[r14,#7*4] |
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266 add r6,r8,r6,ror#2 @ E+=K_xx_xx |
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267 ldr r12,[r14,#2*4] |
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268 eor r9,r9,r10 |
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269 eor r11,r11,r12 @ 1 cycle stall |
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270 eor r10,r4,r5 @ F_xx_xx |
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271 mov r9,r9,ror#31 |
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272 add r6,r6,r7,ror#27 @ E+=ROR(A,27) |
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273 eor r9,r9,r11,ror#31 |
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274 str r9,[r14,#-4]! |
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275 eor r10,r3,r10,ror#2 @ F_xx_xx |
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276 @ F_xx_xx |
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277 add r6,r6,r9 @ E+=X[i] |
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278 add r6,r6,r10 @ E+=F_20_39(B,C,D) |
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279 ldr r9,[r14,#15*4] |
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280 ldr r10,[r14,#13*4] |
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281 ldr r11,[r14,#7*4] |
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282 add r5,r8,r5,ror#2 @ E+=K_xx_xx |
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283 ldr r12,[r14,#2*4] |
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284 eor r9,r9,r10 |
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285 eor r11,r11,r12 @ 1 cycle stall |
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286 eor r10,r3,r4 @ F_xx_xx |
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287 mov r9,r9,ror#31 |
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288 add r5,r5,r6,ror#27 @ E+=ROR(A,27) |
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289 eor r9,r9,r11,ror#31 |
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290 str r9,[r14,#-4]! |
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291 eor r10,r7,r10,ror#2 @ F_xx_xx |
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292 @ F_xx_xx |
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293 add r5,r5,r9 @ E+=X[i] |
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294 add r5,r5,r10 @ E+=F_20_39(B,C,D) |
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295 ldr r9,[r14,#15*4] |
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296 ldr r10,[r14,#13*4] |
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297 ldr r11,[r14,#7*4] |
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298 add r4,r8,r4,ror#2 @ E+=K_xx_xx |
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299 ldr r12,[r14,#2*4] |
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300 eor r9,r9,r10 |
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301 eor r11,r11,r12 @ 1 cycle stall |
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302 eor r10,r7,r3 @ F_xx_xx |
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303 mov r9,r9,ror#31 |
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304 add r4,r4,r5,ror#27 @ E+=ROR(A,27) |
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305 eor r9,r9,r11,ror#31 |
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306 str r9,[r14,#-4]! |
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307 eor r10,r6,r10,ror#2 @ F_xx_xx |
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308 @ F_xx_xx |
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309 add r4,r4,r9 @ E+=X[i] |
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310 add r4,r4,r10 @ E+=F_20_39(B,C,D) |
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311 ldr r9,[r14,#15*4] |
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312 ldr r10,[r14,#13*4] |
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313 ldr r11,[r14,#7*4] |
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314 add r3,r8,r3,ror#2 @ E+=K_xx_xx |
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315 ldr r12,[r14,#2*4] |
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316 eor r9,r9,r10 |
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317 eor r11,r11,r12 @ 1 cycle stall |
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318 eor r10,r6,r7 @ F_xx_xx |
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319 mov r9,r9,ror#31 |
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320 add r3,r3,r4,ror#27 @ E+=ROR(A,27) |
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321 eor r9,r9,r11,ror#31 |
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322 str r9,[r14,#-4]! |
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323 eor r10,r5,r10,ror#2 @ F_xx_xx |
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324 @ F_xx_xx |
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325 add r3,r3,r9 @ E+=X[i] |
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326 add r3,r3,r10 @ E+=F_20_39(B,C,D) |
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327 teq r14,sp @ preserve carry |
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328 bne .L_20_39_or_60_79 @ [+((12+3)*5+2)*4] |
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329 bcs .L_done @ [+((12+3)*5+2)*4], spare 300 bytes |
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330 |
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331 ldr r8,.LK_40_59 |
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332 sub sp,sp,#20*4 @ [+2] |
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333 .L_40_59: |
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334 ldr r9,[r14,#15*4] |
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335 ldr r10,[r14,#13*4] |
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336 ldr r11,[r14,#7*4] |
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337 add r7,r8,r7,ror#2 @ E+=K_xx_xx |
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338 ldr r12,[r14,#2*4] |
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339 eor r9,r9,r10 |
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340 eor r11,r11,r12 @ 1 cycle stall |
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341 eor r10,r5,r6 @ F_xx_xx |
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342 mov r9,r9,ror#31 |
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343 add r7,r7,r3,ror#27 @ E+=ROR(A,27) |
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344 eor r9,r9,r11,ror#31 |
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345 str r9,[r14,#-4]! |
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346 and r10,r4,r10,ror#2 @ F_xx_xx |
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347 and r11,r5,r6 @ F_xx_xx |
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348 add r7,r7,r9 @ E+=X[i] |
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349 add r7,r7,r10 @ E+=F_40_59(B,C,D) |
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350 add r7,r7,r11,ror#2 |
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351 ldr r9,[r14,#15*4] |
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352 ldr r10,[r14,#13*4] |
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353 ldr r11,[r14,#7*4] |
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354 add r6,r8,r6,ror#2 @ E+=K_xx_xx |
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355 ldr r12,[r14,#2*4] |
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356 eor r9,r9,r10 |
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357 eor r11,r11,r12 @ 1 cycle stall |
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358 eor r10,r4,r5 @ F_xx_xx |
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359 mov r9,r9,ror#31 |
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360 add r6,r6,r7,ror#27 @ E+=ROR(A,27) |
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361 eor r9,r9,r11,ror#31 |
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362 str r9,[r14,#-4]! |
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363 and r10,r3,r10,ror#2 @ F_xx_xx |
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364 and r11,r4,r5 @ F_xx_xx |
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365 add r6,r6,r9 @ E+=X[i] |
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366 add r6,r6,r10 @ E+=F_40_59(B,C,D) |
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367 add r6,r6,r11,ror#2 |
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368 ldr r9,[r14,#15*4] |
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369 ldr r10,[r14,#13*4] |
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370 ldr r11,[r14,#7*4] |
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371 add r5,r8,r5,ror#2 @ E+=K_xx_xx |
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372 ldr r12,[r14,#2*4] |
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373 eor r9,r9,r10 |
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374 eor r11,r11,r12 @ 1 cycle stall |
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375 eor r10,r3,r4 @ F_xx_xx |
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376 mov r9,r9,ror#31 |
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377 add r5,r5,r6,ror#27 @ E+=ROR(A,27) |
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378 eor r9,r9,r11,ror#31 |
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379 str r9,[r14,#-4]! |
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380 and r10,r7,r10,ror#2 @ F_xx_xx |
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381 and r11,r3,r4 @ F_xx_xx |
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382 add r5,r5,r9 @ E+=X[i] |
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383 add r5,r5,r10 @ E+=F_40_59(B,C,D) |
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384 add r5,r5,r11,ror#2 |
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385 ldr r9,[r14,#15*4] |
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386 ldr r10,[r14,#13*4] |
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387 ldr r11,[r14,#7*4] |
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388 add r4,r8,r4,ror#2 @ E+=K_xx_xx |
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389 ldr r12,[r14,#2*4] |
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390 eor r9,r9,r10 |
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391 eor r11,r11,r12 @ 1 cycle stall |
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392 eor r10,r7,r3 @ F_xx_xx |
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393 mov r9,r9,ror#31 |
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394 add r4,r4,r5,ror#27 @ E+=ROR(A,27) |
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395 eor r9,r9,r11,ror#31 |
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396 str r9,[r14,#-4]! |
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397 and r10,r6,r10,ror#2 @ F_xx_xx |
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398 and r11,r7,r3 @ F_xx_xx |
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399 add r4,r4,r9 @ E+=X[i] |
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400 add r4,r4,r10 @ E+=F_40_59(B,C,D) |
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401 add r4,r4,r11,ror#2 |
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402 ldr r9,[r14,#15*4] |
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403 ldr r10,[r14,#13*4] |
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404 ldr r11,[r14,#7*4] |
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405 add r3,r8,r3,ror#2 @ E+=K_xx_xx |
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406 ldr r12,[r14,#2*4] |
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407 eor r9,r9,r10 |
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408 eor r11,r11,r12 @ 1 cycle stall |
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|
409 eor r10,r6,r7 @ F_xx_xx |
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410 mov r9,r9,ror#31 |
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411 add r3,r3,r4,ror#27 @ E+=ROR(A,27) |
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412 eor r9,r9,r11,ror#31 |
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413 str r9,[r14,#-4]! |
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414 and r10,r5,r10,ror#2 @ F_xx_xx |
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415 and r11,r6,r7 @ F_xx_xx |
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416 add r3,r3,r9 @ E+=X[i] |
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417 add r3,r3,r10 @ E+=F_40_59(B,C,D) |
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|
418 add r3,r3,r11,ror#2 |
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|
419 teq r14,sp |
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420 bne .L_40_59 @ [+((12+5)*5+2)*4] |
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|
421 |
|
|
422 ldr r8,.LK_60_79 |
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|
423 sub sp,sp,#20*4 |
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|
424 cmp sp,#0 @ set carry to denote 60_79 |
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|
425 b .L_20_39_or_60_79 @ [+4], spare 300 bytes |
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|
426 .L_done: |
|
|
427 add sp,sp,#80*4 @ "deallocate" stack frame |
|
|
428 ldmia r0,{r8,r9,r10,r11,r12} |
|
|
429 add r3,r8,r3 |
|
|
430 add r4,r9,r4 |
|
|
431 add r5,r10,r5,ror#2 |
|
|
432 add r6,r11,r6,ror#2 |
|
|
433 add r7,r12,r7,ror#2 |
|
|
434 stmia r0,{r3,r4,r5,r6,r7} |
|
|
435 teq r1,r2 |
|
|
436 bne .Lloop @ [+18], total 1307 |
|
|
437 |
|
|
438 #if __ARM_ARCH__>=5 |
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|
439 ldmia sp!,{r4-r12,pc} |
|
|
440 #else |
|
|
441 ldmia sp!,{r4-r12,lr} |
|
|
442 tst lr,#1 |
|
|
443 moveq pc,lr @ be binary compatible with V4, yet |
|
|
444 .word 0xe12fff1e @ interoperable with Thumb ISA:-) |
|
|
445 #endif |
|
|
446 .align 2 |
|
|
447 .LK_00_19: .word 0x5a827999 |
|
|
448 .LK_20_39: .word 0x6ed9eba1 |
|
|
449 .LK_40_59: .word 0x8f1bbcdc |
|
|
450 .LK_60_79: .word 0xca62c1d6 |
|
|
451 .size sha1_block_data_order,.-sha1_block_data_order |
|
|
452 .asciz "SHA1 block transform for ARMv4, CRYPTOGAMS by <[email protected]>" |
|
|
453 .align 2 |
