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1 #include <stdio.h> |
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2 #include <string.h> |
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3 #include <stddef.h> |
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4 #include <stdbool.h> |
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5 #include <stdlib.h> |
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6 #include <avr/io.h> |
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7 #include <avr/interrupt.h> |
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8 #include <avr/sleep.h> |
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9 #include <util/delay.h> |
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10 #include <avr/pgmspace.h> |
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11 #include <avr/eeprom.h> |
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12 #include <avr/wdt.h> |
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13 #include <util/atomic.h> |
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14 #include <util/crc16.h> |
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15 |
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16 #include "hmac-sha1.h" |
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17 #include "aes.h" |
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18 |
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19 //#include "simple_ds18b20.h" |
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20 //#include "onewire.h" |
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21 |
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5
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22 LOCKBITS = (LB_MODE_3 & BLB0_MODE_4 & BLB1_MODE_4); |
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23 |
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24 #define MIN(X,Y) ((X) < (Y) ? (X) : (Y)) |
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25 #define MAX(X,Y) ((X) > (Y) ? (X) : (Y)) |
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26 |
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27 // TICK should be 8 or less (8 untested). all timers need |
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28 // to be a multiple. |
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29 |
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30 #define TICK 1 |
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31 #define SLEEP_COMPARE (2000000/64) // == 31250 exactly |
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32 #define NKEYS 10 |
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33 #define HMACLEN 20 |
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34 #define AESLEN 16 |
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35 #define KEYLEN HMACLEN |
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36 |
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37 #define BAUD 19200 |
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38 #define UBRR ((F_CPU)/8/(BAUD)-1) |
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39 |
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40 #define PORT_PI_BOOT PORTD |
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41 #define DDR_PI_BOOT DDRD |
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42 #define PIN_PI_BOOT PD5 |
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43 |
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44 #define PORT_PI_RESET PORTD |
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45 #define DDR_PI_RESET DDRD |
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46 #define PIN_PI_RESET PD6 |
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47 |
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4
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48 #define PORT_LED PORTD |
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49 #define DDR_LED DDRD |
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50 #define PIN_LED PD7 |
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51 |
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52 // #define HAVE_UART_ECHO |
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53 |
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7
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54 // stores a value of clock_epoch combined with the remainder of TCNT1, |
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55 // for 1/32 second accuracy |
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56 struct epoch_ticks |
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57 { |
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58 uint32_t ticks; |
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59 // remainder |
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60 uint8_t rem; |
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61 }; |
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62 |
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63 // eeprom-settable parameters, default values defined here. |
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64 // all timeouts should be a multiple of TICK |
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65 static uint32_t watchdog_long_limit = (60L*60*24); |
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66 static uint32_t watchdog_short_limit = 0; |
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67 static uint32_t newboot_limit = 60*10; |
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68 |
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69 // avr proves itself |
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70 static uint8_t avr_keys[NKEYS][KEYLEN] = {{0}}; |
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71 |
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72 // ---- Atomic guards required accessing these variables |
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73 // clock_epoch in seconds |
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74 static uint32_t clock_epoch; |
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75 // watchdog counts up |
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76 static uint32_t watchdog_long_count; |
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77 static uint32_t watchdog_short_count; |
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78 // newboot counts down |
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79 static uint32_t newboot_count; |
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80 // oneshot counts down |
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81 static uint32_t oneshot_count; |
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82 |
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83 // ---- End atomic guards required |
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84 |
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85 // boolean flags |
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86 static uint8_t watchdog_long_hit; |
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87 static uint8_t watchdog_short_hit; |
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88 static uint8_t newboot_hit; |
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89 static uint8_t oneshot_hit; |
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90 |
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91 static uint8_t readpos; |
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92 static char readbuf[50]; |
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93 static uint8_t have_cmd; |
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94 |
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95 int uart_putchar(char c, FILE *stream); |
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96 static void long_delay(int ms); |
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97 static void blink(); |
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98 static uint16_t adc_vcc(); |
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99 static void set_pi_boot_normal(uint8_t normal); |
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100 |
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101 static FILE mystdout = FDEV_SETUP_STREAM(uart_putchar, NULL, |
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102 _FDEV_SETUP_WRITE); |
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103 |
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104 // thanks to http://projectgus.com/2010/07/eeprom-access-with-arduino/ |
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105 #define eeprom_read_to(dst_p, eeprom_field, dst_size) eeprom_read_block((dst_p), (void *)offsetof(struct __eeprom_data, eeprom_field), (dst_size)) |
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106 #define eeprom_read(dst, eeprom_field) eeprom_read_to((&dst), eeprom_field, sizeof(dst)) |
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107 #define eeprom_write_from(src_p, eeprom_field, src_size) eeprom_write_block((src_p), (void *)offsetof(struct __eeprom_data, eeprom_field), (src_size)) |
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108 #define eeprom_write(src, eeprom_field) { eeprom_write_from(&src, eeprom_field, sizeof(src)); } |
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109 |
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110 #define EXPECT_MAGIC 0xdf83 |
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111 |
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112 struct __attribute__ ((__packed__)) __eeprom_data { |
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113 uint32_t watchdog_long_limit; |
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114 uint32_t watchdog_short_limit; |
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115 uint32_t newboot_limit; |
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116 |
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117 uint8_t avr_keys[NKEYS][KEYLEN]; |
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118 |
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119 uint16_t magic; |
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120 }; |
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121 |
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122 // Very first setup |
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123 static void |
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124 setup_chip() |
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125 { |
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126 cli(); |
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127 |
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128 // stop watchdog timer (might have been used to cause a reset) |
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129 wdt_reset(); |
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130 MCUSR &= ~_BV(WDRF); |
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131 WDTCSR |= _BV(WDCE) | _BV(WDE); |
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132 WDTCSR = 0; |
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133 |
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134 // set to 8S, in case sha1 is slow etc. |
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135 wdt_enable(WDTO_8S); |
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136 |
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137 // Set clock to 2mhz |
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138 CLKPR = _BV(CLKPCE); |
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139 CLKPR = _BV(CLKPS1); |
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140 |
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141 // enable pullups |
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142 // XXX matt pihelp |
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143 //PORTB = 0xff; // XXX change when using SPI |
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144 //PORTD = 0xff; |
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145 //PORTC = 0xff; |
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146 |
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147 // 3.3v power for bluetooth and SD |
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148 DDR_LED |= _BV(PIN_LED); |
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149 |
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150 #if 0 |
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151 // set pullup |
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152 PORTD |= _BV(PD2); |
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153 // INT0 setup |
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154 EICRA = (1<<ISC01); // falling edge - data sheet says it won't work? |
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155 EIMSK = _BV(INT0); |
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156 #endif |
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157 |
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158 // comparator disable |
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159 ACSR = _BV(ACD); |
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160 |
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161 // disable adc pin input buffers |
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162 DIDR0 = 0x3F; // acd0-adc5 |
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163 DIDR1 = (1<<AIN1D)|(1<<AIN0D); // ain0/ain1 |
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164 |
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165 sei(); |
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166 } |
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167 |
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168 static void |
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169 get_epoch_ticks(struct epoch_ticks *t) |
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170 { |
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171 ATOMIC_BLOCK(ATOMIC_RESTORESTATE) |
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172 { |
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173 t->ticks = clock_epoch; |
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174 t->rem = TCNT1; |
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175 } |
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176 } |
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177 |
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178 static void |
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179 setup_tick_counter() |
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180 { |
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181 // set up counter1 |
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182 |
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183 // set up counter2. |
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184 // COM21 COM20 Set OC2 on Compare Match (p116) |
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185 // WGM21 Clear counter on compare |
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186 //TCCR2A = _BV(COM2A1) | _BV(COM2A0) | _BV(WGM21); |
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187 // toggle on match |
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188 TCCR1A = _BV(COM1A0); |
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189 // systemclock/64 |
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190 TCCR1B = _BV(CS11) | _BV(CS10); |
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191 TCNT1 = 0; |
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192 OCR1A = SLEEP_COMPARE; |
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193 // interrupt |
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194 TIMSK1 = _BV(OCIE1A); |
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195 } |
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196 |
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197 static void |
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198 uart_on() |
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199 { |
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200 // Power reduction register |
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201 PRR &= ~_BV(PRUSART0); |
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202 |
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203 // All of this needs to be done each time after turning off the PRR |
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204 // baud rate |
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205 UBRR0H = (unsigned char)(UBRR >> 8); |
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206 UBRR0L = (unsigned char)UBRR; |
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207 // set 2x clock, improves accuracy of UBRR |
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208 UCSR0A |= _BV(U2X0); |
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209 UCSR0B = _BV(RXCIE0) | _BV(RXEN0) | _BV(TXEN0); |
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210 //8N1 |
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211 UCSR0C = _BV(UCSZ01) | _BV(UCSZ00); |
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212 } |
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213 |
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214 static void |
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215 uart_off() |
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216 { |
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217 // Turn off interrupts and disable tx/rx |
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218 UCSR0B = 0; |
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219 |
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220 // Power reduction register |
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221 PRR |= _BV(PRUSART0); |
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222 } |
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223 |
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224 int |
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225 uart_putchar(char c, FILE *stream) |
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226 { |
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227 // XXX could perhaps sleep in the loop for power. |
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228 if (c == '\n') |
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229 { |
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230 loop_until_bit_is_set(UCSR0A, UDRE0); |
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231 UDR0 = '\r'; |
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232 } |
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233 loop_until_bit_is_set(UCSR0A, UDRE0); |
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234 UDR0 = c; |
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235 if (c == '\r') |
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236 { |
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237 loop_until_bit_is_set(UCSR0A, UDRE0); |
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238 UDR0 = '\n'; |
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239 } |
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240 return (unsigned char)c; |
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241 } |
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242 |
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243 static void |
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244 cmd_reset() |
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245 { |
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246 printf_P(PSTR("reset\n")); |
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247 _delay_ms(100); |
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248 cli(); // disable interrupts |
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249 wdt_enable(WDTO_15MS); // enable watchdog |
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250 while(1); // wait for watchdog to reset processor |
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251 } |
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252 |
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253 static void |
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254 cmd_newboot() |
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255 { |
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256 set_pi_boot_normal(1); |
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257 ATOMIC_BLOCK(ATOMIC_RESTORESTATE) |
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258 { |
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259 newboot_count = newboot_limit; |
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260 } |
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261 printf_P(PSTR("newboot for %d secs"), newboot_limit); |
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262 } |
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263 |
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264 |
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265 |
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266 static void |
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267 cmd_get_params() |
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268 { |
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269 uint32_t cur_watchdog_long, cur_watchdog_short, cur_newboot, cur_oneshot; |
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270 ATOMIC_BLOCK(ATOMIC_RESTORESTATE) |
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271 { |
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272 cur_watchdog_long = watchdog_long_count; |
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273 cur_watchdog_short = watchdog_short_count; |
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274 cur_newboot = newboot_count; |
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275 cur_oneshot = oneshot_count; |
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276 } |
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277 |
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278 printf_P(PSTR("limit (count) : watchdog_long %lu (%lu) watchdog_short %lu (%lu) newboot %lu (%lu) oneshot (%lu)\n"), |
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279 watchdog_long_limit, |
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280 cur_watchdog_long, |
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281 watchdog_short_limit, |
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282 cur_watchdog_short, |
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283 newboot_limit, |
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284 cur_newboot, |
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285 cur_oneshot); |
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286 } |
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287 |
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288 static void |
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289 cmd_set_params(const char *params) |
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290 { |
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291 uint32_t new_watchdog_long_limit; |
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292 uint32_t new_watchdog_short_limit; |
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293 uint32_t new_newboot_limit; |
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294 |
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295 int ret = sscanf_P(params, PSTR("%lu %lu %lu"), |
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296 &new_watchdog_long_limit, |
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297 &new_watchdog_short_limit, |
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298 &new_newboot_limit); |
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299 |
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300 |
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301 if (ret != 3) |
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302 { |
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303 printf_P(PSTR("Bad values\n")); |
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304 } |
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305 else |
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306 { |
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307 ATOMIC_BLOCK(ATOMIC_RESTORESTATE) |
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308 { |
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309 eeprom_write(new_watchdog_long_limit, watchdog_long_limit); |
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310 eeprom_write(new_watchdog_short_limit, watchdog_short_limit); |
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311 eeprom_write(new_newboot_limit, newboot_limit); |
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312 uint16_t magic = EXPECT_MAGIC; |
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313 eeprom_write(magic, magic); |
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0
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314 } |
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1
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315 printf_P(PSTR("set_params for next boot\n")); |
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316 printf_P(PSTR("watchdog_long %lu watchdog_short %lu newboot %lu\n"), |
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317 new_watchdog_long_limit, |
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318 new_watchdog_short_limit, |
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319 new_newboot_limit); |
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320 |
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321 } |
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322 } |
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0
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323 |
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1
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324 uint8_t from_hex(char c) |
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325 { |
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326 if (c >= '0' && c <= '9') { |
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327 return c-'0'; |
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328 } |
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329 if (c >= 'a' && c <= 'f') { |
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330 return c-'a' + 0xa; |
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331 } |
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332 if (c >= 'A' && c <= 'F') { |
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333 return c-'A' + 0xa; |
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334 } |
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335 return 0; |
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336 } |
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337 |
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2
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338 static void |
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339 printhex_nibble(const unsigned char b, FILE *stream) |
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340 { |
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341 unsigned char c = b & 0x0f; |
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342 if ( c > 9 ) { |
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343 c += 'A'-10; |
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344 } |
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345 else { |
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346 c += '0'; |
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347 } |
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348 fputc(c, stream); |
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349 } |
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350 |
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351 void |
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352 printhex_byte(const unsigned char b, FILE *stream) |
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353 { |
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354 printhex_nibble( b >> 4, stream); |
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355 printhex_nibble( b, stream); |
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356 } |
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357 |
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358 void |
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359 printhex(uint8_t *id, uint8_t n, FILE *stream) |
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360 { |
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361 for (uint8_t i = 0; i < n; i++) |
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362 { |
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363 if (i > 0) |
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364 { |
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365 fputc(' ', stream); |
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366 } |
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367 printhex_byte(id[i], stream); |
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368 } |
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369 } |
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370 |
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371 static int8_t |
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5
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372 parse_key(const char *params, uint8_t *key_index, uint8_t *bytes, |
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373 uint8_t bytes_len) |
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2
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374 { |
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375 // "N HEXKEY" |
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5
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376 if (strlen(params) != bytes_len*2 + 2) { |
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2
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377 printf_P(PSTR("Wrong length key\n")); |
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378 return -1; |
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379 } |
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380 |
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381 if (params[1] != ' ') |
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382 { |
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383 printf_P(PSTR("Missing space\n")); |
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384 return -1; |
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385 } |
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386 |
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387 *key_index = from_hex(params[0]); |
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388 if (*key_index >= NKEYS) |
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389 { |
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390 printf_P(PSTR("Bad key index %d, max %d\n"), *key_index, NKEYS); |
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391 return -1; |
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392 } |
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393 |
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5
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394 for (int i = 0, p = 0; i < bytes_len; i++, p += 2) |
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2
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395 { |
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396 bytes[i] = (from_hex(params[p+2]) << 4) | from_hex(params[p+3]); |
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397 } |
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398 return 0; |
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399 } |
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400 |
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1
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401 static void |
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402 cmd_set_avr_key(const char *params) |
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403 { |
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2
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404 uint8_t new_key[KEYLEN]; |
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405 uint8_t key_index; |
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5
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406 if (parse_key(params, &key_index, new_key, sizeof(new_key)) != 0) |
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2
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407 { |
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1
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408 return; |
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0
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409 } |
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2
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410 memcpy(avr_keys[key_index], new_key, sizeof(new_key)); |
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411 eeprom_write(avr_keys, avr_keys); |
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412 } |
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413 |
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414 static void |
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415 cmd_hmac(const char *params) |
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416 { |
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7
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417 uint8_t indata[HMACLEN]; |
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418 uint8_t outdata[HMACLEN]; |
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2
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419 uint8_t key_index; |
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7
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420 if (parse_key(params, &key_index, indata, sizeof(indata)) != 0) |
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2
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421 { |
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422 printf_P(PSTR("FAIL: Bad input\n")); |
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5
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423 return; |
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2
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424 } |
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0
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425 |
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7
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426 if (key_index % 2 != 0) |
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5
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427 { |
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428 printf_P(PSTR("Only hmac with even keys\n")); |
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429 return; |
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430 } |
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431 |
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432 long_delay(200); |
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433 |
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7
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434 hmac_sha1(outdata, avr_keys[key_index], KEYLEN*8, indata, HMACLEN*8); |
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2
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435 |
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436 printf_P(PSTR("HMAC: ")); |
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7
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437 printhex(outdata, HMACLEN, stdout); |
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5
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438 fputc('\n', stdout); |
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439 } |
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440 |
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441 static void |
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442 cmd_decrypt(const char *params) |
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443 { |
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444 uint8_t data[HMACLEN+AESLEN]; |
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445 uint8_t output[HMACLEN]; |
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446 uint8_t key_index; |
|
|
447 if (parse_key(params, &key_index, data, sizeof(data)) != 0) |
|
|
448 { |
|
|
449 printf_P(PSTR("FAIL: Bad input\n")); |
|
|
450 return; |
|
|
451 } |
|
|
452 |
|
7
|
453 if (key_index % 2 == 0) |
|
5
|
454 { |
|
|
455 printf_P(PSTR("Only decrypt with odd keys\n")); |
|
|
456 return; |
|
|
457 } |
|
|
458 |
|
|
459 long_delay(200); |
|
|
460 |
|
7
|
461 |
|
5
|
462 // check the signature |
|
7
|
463 hmac_sha1(output, avr_keys[key_index], KEYLEN*8, &data[HMACLEN], AESLEN*8); |
|
5
|
464 |
|
|
465 if (memcmp(output, data, HMACLEN) != 0) { |
|
|
466 printf_P(PSTR("FAIL: hmac mismatch\n")); |
|
|
467 } |
|
|
468 |
|
|
469 uint8_t expkey[AES_EXPKEY_SIZE]; |
|
|
470 ExpandKey(avr_keys[key_index], expkey); |
|
|
471 Decrypt(&data[HMACLEN], expkey, output); |
|
|
472 |
|
|
473 printf_P(PSTR("DECRYPTED: ")); |
|
|
474 printhex(output, AESLEN, stdout); |
|
2
|
475 fputc('\n', stdout); |
|
|
476 } |
|
|
477 |
|
|
478 static void |
|
|
479 cmd_oneshot_reboot(const char *params) |
|
|
480 { |
|
|
481 uint32_t new_delay = strtoul(params, NULL, 10); |
|
|
482 ATOMIC_BLOCK(ATOMIC_RESTORESTATE) |
|
1
|
483 { |
|
2
|
484 oneshot_count = new_delay; |
|
1
|
485 } |
|
2
|
486 printf_P(PSTR("oneshot delay %lu\n"), new_delay); |
|
0
|
487 } |
|
|
488 |
|
|
489 static void |
|
|
490 load_params() |
|
|
491 { |
|
|
492 uint16_t magic; |
|
|
493 eeprom_read(magic, magic); |
|
|
494 if (magic == EXPECT_MAGIC) |
|
|
495 { |
|
1
|
496 eeprom_read(watchdog_long_limit, watchdog_long_limit); |
|
|
497 eeprom_read(watchdog_short_limit, watchdog_short_limit); |
|
2
|
498 eeprom_read(newboot_limit, newboot_limit); |
|
1
|
499 } |
|
2
|
500 |
|
|
501 eeprom_read(avr_keys, avr_keys); |
|
0
|
502 } |
|
|
503 |
|
2
|
504 static void |
|
|
505 cmd_vcc() |
|
0
|
506 { |
|
2
|
507 uint16_t vcc = adc_vcc(); |
|
|
508 printf_P("vcc: %u mV\n", vcc); |
|
0
|
509 } |
|
|
510 |
|
|
511 static void |
|
|
512 read_handler() |
|
|
513 { |
|
2
|
514 if (strcmp_P(readbuf, PSTR("get_params")) == 0) |
|
0
|
515 { |
|
|
516 cmd_get_params(); |
|
|
517 } |
|
|
518 else if (strncmp_P(readbuf, PSTR("set_params "), 11) == 0) |
|
|
519 { |
|
|
520 cmd_set_params(&readbuf[11]); |
|
|
521 } |
|
2
|
522 else if (strncmp_P(readbuf, PSTR("set_key "), 8) == 0) |
|
0
|
523 { |
|
2
|
524 cmd_set_avr_key(&readbuf[8]); |
|
0
|
525 } |
|
2
|
526 else if (strncmp_P(readbuf, PSTR("oneshot "), 8) == 0) |
|
0
|
527 { |
|
2
|
528 cmd_oneshot_reboot(&readbuf[8]); |
|
0
|
529 } |
|
2
|
530 else if (strncmp_P(readbuf, PSTR("hmac "), 5) == 0) |
|
0
|
531 { |
|
2
|
532 cmd_hmac(&readbuf[5]); |
|
0
|
533 } |
|
5
|
534 else if (strncmp_P(readbuf, PSTR("decrypt "), 8) == 0) |
|
|
535 { |
|
|
536 cmd_hmac(&readbuf[8]); |
|
|
537 } |
|
2
|
538 else if (strcmp_P(readbuf, PSTR("vcc")) == 0) |
|
0
|
539 { |
|
2
|
540 cmd_vcc(); |
|
0
|
541 } |
|
|
542 else if (strcmp_P(readbuf, PSTR("reset")) == 0) |
|
|
543 { |
|
|
544 cmd_reset(); |
|
|
545 } |
|
4
|
546 else if (strcmp_P(readbuf, PSTR("newboot")) == 0) |
|
|
547 { |
|
|
548 cmd_newboot(); |
|
|
549 } |
|
0
|
550 else |
|
|
551 { |
|
|
552 printf_P(PSTR("Bad command '%s'\n"), readbuf); |
|
|
553 } |
|
|
554 } |
|
|
555 |
|
|
556 ISR(INT0_vect) |
|
|
557 { |
|
|
558 blink(); |
|
|
559 _delay_ms(100); |
|
|
560 blink(); |
|
|
561 } |
|
|
562 |
|
|
563 ISR(USART_RX_vect) |
|
|
564 { |
|
|
565 char c = UDR0; |
|
|
566 #ifdef HAVE_UART_ECHO |
|
|
567 uart_putchar(c, NULL); |
|
|
568 #endif |
|
|
569 if (c == '\r' || c == '\n') |
|
|
570 { |
|
|
571 if (readpos > 0) |
|
|
572 { |
|
|
573 readbuf[readpos] = '\0'; |
|
|
574 have_cmd = 1; |
|
|
575 readpos = 0; |
|
|
576 } |
|
|
577 } |
|
|
578 else |
|
|
579 { |
|
|
580 readbuf[readpos] = c; |
|
|
581 readpos++; |
|
|
582 if (readpos >= sizeof(readbuf)) |
|
|
583 { |
|
|
584 readpos = 0; |
|
|
585 } |
|
|
586 } |
|
|
587 } |
|
|
588 |
|
2
|
589 ISR(TIMER1_COMPA_vect) |
|
0
|
590 { |
|
2
|
591 TCNT1 = 0; |
|
0
|
592 |
|
|
593 clock_epoch += TICK; |
|
|
594 |
|
1
|
595 // watchdogs count up, continuous |
|
|
596 if (watchdog_long_limit > 0) { |
|
2
|
597 watchdog_long_count += TICK; |
|
1
|
598 if (watchdog_long_count >= watchdog_long_limit) |
|
|
599 { |
|
|
600 watchdog_long_count = 0; |
|
|
601 watchdog_long_hit = 1; |
|
|
602 } |
|
0
|
603 } |
|
|
604 |
|
1
|
605 if (watchdog_short_limit > 0) { |
|
2
|
606 watchdog_short_count += TICK; |
|
1
|
607 if (watchdog_short_count >= watchdog_short_limit) |
|
|
608 { |
|
|
609 watchdog_short_count = 0; |
|
|
610 watchdog_short_hit = 1; |
|
|
611 } |
|
0
|
612 } |
|
|
613 |
|
2
|
614 // newboot counts down |
|
1
|
615 if (newboot_count > 0) |
|
0
|
616 { |
|
2
|
617 newboot_count-=TICK; |
|
|
618 if (newboot_count <= 0) |
|
1
|
619 { |
|
|
620 newboot_hit = 1; |
|
2
|
621 newboot_count = 0; |
|
1
|
622 } |
|
0
|
623 } |
|
1
|
624 |
|
2
|
625 if (oneshot_count > 0) |
|
|
626 { |
|
|
627 oneshot_count-=TICK; |
|
|
628 if (oneshot_count <= 0) |
|
|
629 { |
|
|
630 oneshot_hit = 1; |
|
|
631 oneshot_count = 0; |
|
|
632 } |
|
|
633 } |
|
0
|
634 } |
|
|
635 |
|
|
636 static void |
|
|
637 idle_sleep() |
|
|
638 { |
|
|
639 set_sleep_mode(SLEEP_MODE_IDLE); |
|
|
640 sleep_mode(); |
|
|
641 } |
|
|
642 |
|
|
643 static uint16_t |
|
|
644 adc_vcc() |
|
|
645 { |
|
|
646 PRR &= ~_BV(PRADC); |
|
|
647 |
|
|
648 // /16 prescaler |
|
|
649 ADCSRA = _BV(ADEN) | _BV(ADPS2); |
|
|
650 |
|
|
651 // set to measure 1.1 reference |
|
|
652 ADMUX = _BV(REFS0) | _BV(MUX3) | _BV(MUX2) | _BV(MUX1); |
|
|
653 // average a number of samples |
|
|
654 uint16_t sum = 0; |
|
|
655 uint8_t num = 0; |
|
|
656 for (uint8_t n = 0; n < 20; n++) |
|
|
657 { |
|
|
658 ADCSRA |= _BV(ADSC); |
|
|
659 loop_until_bit_is_clear(ADCSRA, ADSC); |
|
|
660 |
|
|
661 uint8_t low_11 = ADCL; |
|
|
662 uint8_t high_11 = ADCH; |
|
|
663 uint16_t val = low_11 + (high_11 << 8); |
|
|
664 |
|
|
665 if (n >= 4) |
|
|
666 { |
|
|
667 sum += val; |
|
|
668 num++; |
|
|
669 } |
|
|
670 } |
|
|
671 ADCSRA = 0; |
|
|
672 PRR |= _BV(PRADC); |
|
|
673 |
|
|
674 //float res_volts = 1.1 * 1024 * num / sum; |
|
|
675 //return 1000 * res_volts; |
|
|
676 return ((uint32_t)1100*1024*num) / sum; |
|
|
677 } |
|
|
678 |
|
|
679 static void |
|
2
|
680 reboot_pi() |
|
|
681 { |
|
|
682 // pull it low for 30ms |
|
|
683 PORT_PI_RESET &= ~_BV(PIN_PI_RESET); |
|
|
684 DDR_PI_RESET |= _BV(PIN_PI_RESET); |
|
|
685 _delay_ms(30); |
|
|
686 DDR_PI_RESET &= ~_BV(PIN_PI_RESET); |
|
|
687 } |
|
|
688 |
|
|
689 static void |
|
|
690 set_pi_boot_normal(uint8_t normal) |
|
|
691 { |
|
|
692 PORT_PI_BOOT &= ~_BV(PIN_PI_BOOT); |
|
|
693 if (normal) |
|
|
694 { |
|
|
695 // tristate |
|
|
696 DDR_PI_BOOT &= ~_BV(PIN_PI_BOOT); |
|
|
697 } |
|
|
698 else |
|
|
699 { |
|
|
700 // pull it low |
|
|
701 DDR_PI_RESET |= _BV(PIN_PI_BOOT); |
|
|
702 |
|
|
703 } |
|
|
704 } |
|
|
705 |
|
|
706 static void |
|
|
707 check_flags() |
|
|
708 { |
|
|
709 if (watchdog_long_hit |
|
|
710 || watchdog_short_hit |
|
|
711 || oneshot_hit) |
|
|
712 { |
|
|
713 reboot_pi(); |
|
|
714 } |
|
|
715 |
|
|
716 if (newboot_hit) { |
|
|
717 set_pi_boot_normal(0); |
|
|
718 } |
|
|
719 |
|
|
720 watchdog_long_hit = 0; |
|
|
721 watchdog_short_hit = 0; |
|
|
722 newboot_hit = 0; |
|
|
723 oneshot_hit = 0; |
|
|
724 } |
|
|
725 |
|
|
726 static void |
|
0
|
727 do_comms() |
|
|
728 { |
|
|
729 // avoid receiving rubbish, perhaps |
|
|
730 uart_on(); |
|
|
731 |
|
|
732 // write sd card here? same 3.3v regulator... |
|
|
733 |
|
1
|
734 while (1) |
|
0
|
735 { |
|
1
|
736 wdt_reset(); |
|
2
|
737 |
|
|
738 check_flags(); |
|
|
739 |
|
0
|
740 if (have_cmd) |
|
|
741 { |
|
|
742 have_cmd = 0; |
|
|
743 read_handler(); |
|
|
744 continue; |
|
|
745 } |
|
|
746 |
|
|
747 // wait for commands from the master |
|
|
748 idle_sleep(); |
|
|
749 } |
|
|
750 } |
|
|
751 |
|
|
752 static void |
|
|
753 blink() |
|
|
754 { |
|
|
755 PORT_LED &= ~_BV(PIN_LED); |
|
|
756 _delay_ms(1); |
|
|
757 PORT_LED |= _BV(PIN_LED); |
|
|
758 } |
|
|
759 |
|
|
760 static void |
|
|
761 long_delay(int ms) |
|
|
762 { |
|
|
763 int iter = ms / 100; |
|
|
764 |
|
|
765 for (int i = 0; i < iter; i++) |
|
|
766 { |
|
|
767 _delay_ms(100); |
|
|
768 } |
|
|
769 } |
|
|
770 |
|
|
771 ISR(BADISR_vect) |
|
|
772 { |
|
|
773 //uart_on(); |
|
|
774 printf_P(PSTR("Bad interrupt\n")); |
|
|
775 } |
|
|
776 |
|
|
777 int main(void) |
|
|
778 { |
|
|
779 setup_chip(); |
|
|
780 blink(); |
|
|
781 |
|
|
782 stdout = &mystdout; |
|
|
783 uart_on(); |
|
|
784 |
|
5
|
785 printf(PSTR("Pi Watchdog\nMatt Johnston [email protected]")); |
|
0
|
786 |
|
2
|
787 set_pi_boot_normal(0); |
|
|
788 |
|
0
|
789 load_params(); |
|
|
790 |
|
|
791 setup_tick_counter(); |
|
|
792 |
|
|
793 sei(); |
|
|
794 |
|
1
|
795 // doesn't return |
|
|
796 do_comms(); |
|
0
|
797 |
|
|
798 return 0; /* never reached */ |
|
|
799 } |
