Mercurial > pihelp
changeset 44:2a47c458d6ed
a bit of debugging tht didn't work
| author | Matt Johnston <matt@ucc.asn.au> |
|---|---|
| date | Sat, 29 Jun 2013 23:46:35 +0800 |
| parents | 69cbf9ce72b5 |
| children | a0f2fcc6d9dd |
| files | sd_raw.c sd_raw_config.h |
| diffstat | 2 files changed, 61 insertions(+), 6 deletions(-) [+] |
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--- a/sd_raw.c Sat Jun 29 10:42:34 2013 +0800 +++ b/sd_raw.c Sat Jun 29 23:46:35 2013 +0800 @@ -10,6 +10,9 @@ #include <string.h> #include <avr/io.h> +#include <util/delay.h> +#include <avr/pgmspace.h> +#include <stdio.h> #include "sd_raw.h" /** @@ -163,6 +166,8 @@ static uint8_t sd_raw_rec_byte(); static uint8_t sd_raw_send_command(uint8_t command, uint32_t arg); +static uint8_t orig_pb; + /** * \ingroup sd_raw * Initializes memory card communication. @@ -175,6 +180,15 @@ configure_pin_available(); configure_pin_locked(); + orig_pb = PORTB; + + printf_P(PSTR("startup portb %hhx mosi %d, sck %d, ss, miso %d\n"), + PORTB, + orig_pb & _BV(PB3), + orig_pb & _BV(PB5), + orig_pb & _BV(PB2), + orig_pb & _BV(PB4)); + /* enable outputs for MOSI, SCK, SS, input for MISO */ configure_pin_mosi(); configure_pin_sck(); @@ -333,9 +347,49 @@ void sd_raw_deinit(void) { - configure_pin_mosi(); - configure_pin_sck(); - configure_pin_ss(); + + printf_P(PSTR("deinit mosi %d, sck %d, ss, miso %d\n"), + PORTB & _BV(PB3), + PORTB & _BV(PB5), + PORTB & _BV(PB2), + PORTB & _BV(PB4)); + + // set to slave mode + SPCR = (0 << SPIE) | /* SPI Interrupt Enable */ + (1 << SPE) | /* SPI Enable */ + (0 << DORD) | /* Data Order: MSB first */ + (0 << MSTR) | /* Master mode */ + (0 << CPOL) | /* Clock Polarity: SCK low when idle */ + (0 << CPHA) | /* Clock Phase: sample on rising SCK edge */ + (1 << SPR1) | /* Clock Frequency: f_OSC / 128 */ + (1 << SPR0); + + _delay_ms(15); + + // disable it + SPCR = (0 << SPIE) | /* SPI Interrupt Enable */ + (0 << SPE) | /* SPI Enable */ + (0 << DORD) | /* Data Order: MSB first */ + (0 << MSTR) | /* Master mode */ + (0 << CPOL) | /* Clock Polarity: SCK low when idle */ + (0 << CPHA) | /* Clock Phase: sample on rising SCK edge */ + (1 << SPR1) | /* Clock Frequency: f_OSC / 128 */ + (1 << SPR0); + + _delay_ms(15); + + uint8_t pb_mask = _BV(PB3) | _BV(PB5) | _BV(PB2); + printf_P(PSTR("PORTB was %hhx\n"), + PORTB); + PORTB = (PORTB & ~pb_mask) | (orig_pb & pb_mask); + printf_P(PSTR("PORTB now %hhx\n"), + PORTB); + + _delay_ms(15); + + deconfigure_pin_mosi(); + deconfigure_pin_sck(); + deconfigure_pin_ss(); } /**
--- a/sd_raw_config.h Sat Jun 29 10:42:34 2013 +0800 +++ b/sd_raw_config.h Sat Jun 29 23:46:35 2013 +0800 @@ -85,9 +85,10 @@ #define configure_pin_ss() DDRB |= (1 << DDB2) #define configure_pin_miso() DDRB &= ~(1 << DDB4) - #define deonfigure_pin_mosi() DDRB &= ~(1 << DDB3) - #define deonfigure_pin_sck() DDRB &= ~(1 << DDB5) - #define deonfigure_pin_ss() DDRB &= ~(1 << DDB2) + #define deconfigure_pin_mosi() DDRB &= ~(1 << DDB3) + #define deconfigure_pin_sck() DDRB &= ~(1 << DDB5) + #define deconfigure_pin_ss() DDRB &= ~(1 << DDB2) + #define select_card() PORTB &= ~(1 << PORTB2) #define unselect_card() PORTB |= (1 << PORTB2)