Mercurial > pihelp
annotate main.c @ 16:8b1aeff120e9
add max/min sanity checks
| author | Matt Johnston <matt@ucc.asn.au> |
|---|---|
| date | Thu, 13 Jun 2013 00:22:37 +0800 |
| parents | 915be6f0ff13 |
| children | 21717153e0f1 |
| rev | line source |
|---|---|
| 0 | 1 #include <stdio.h> |
| 2 #include <string.h> | |
| 3 #include <stddef.h> | |
| 4 #include <stdbool.h> | |
| 5 #include <stdlib.h> | |
| 6 #include <avr/io.h> | |
| 7 #include <avr/interrupt.h> | |
| 8 #include <avr/sleep.h> | |
| 9 #include <util/delay.h> | |
| 10 #include <avr/pgmspace.h> | |
| 11 #include <avr/eeprom.h> | |
| 12 #include <avr/wdt.h> | |
| 13 #include <util/atomic.h> | |
| 14 #include <util/crc16.h> | |
| 15 | |
| 2 | 16 #include "hmac-sha1.h" |
| 5 | 17 #include "aes.h" |
| 2 | 18 |
| 1 | 19 //#include "simple_ds18b20.h" |
| 20 //#include "onewire.h" | |
| 0 | 21 |
| 5 | 22 LOCKBITS = (LB_MODE_3 & BLB0_MODE_4 & BLB1_MODE_4); |
| 23 | |
| 0 | 24 #define MIN(X,Y) ((X) < (Y) ? (X) : (Y)) |
| 25 #define MAX(X,Y) ((X) > (Y) ? (X) : (Y)) | |
| 26 | |
| 27 // TICK should be 8 or less (8 untested). all timers need | |
| 28 // to be a multiple. | |
| 29 | |
| 1 | 30 #define TICK 1 |
| 2 | 31 #define SLEEP_COMPARE (2000000/64) // == 31250 exactly |
|
15
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
32 #define COUNTER_DIV (F_CPU / 2000000) |
| 5 | 33 #define NKEYS 10 |
| 34 #define HMACLEN 20 | |
| 35 #define AESLEN 16 | |
| 36 #define KEYLEN HMACLEN | |
| 1 | 37 |
|
15
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
38 #define BAUD 38400 |
| 0 | 39 #define UBRR ((F_CPU)/8/(BAUD)-1) |
| 40 | |
| 2 | 41 #define PORT_PI_BOOT PORTD |
| 42 #define DDR_PI_BOOT DDRD | |
| 4 | 43 #define PIN_PI_BOOT PD5 |
| 2 | 44 |
| 45 #define PORT_PI_RESET PORTD | |
| 46 #define DDR_PI_RESET DDRD | |
| 47 #define PIN_PI_RESET PD6 | |
| 48 | |
| 4 | 49 #define PORT_LED PORTD |
| 50 #define DDR_LED DDRD | |
| 51 #define PIN_LED PD7 | |
| 0 | 52 |
| 53 // #define HAVE_UART_ECHO | |
| 54 | |
| 7 | 55 // stores a value of clock_epoch combined with the remainder of TCNT1, |
| 0 | 56 // for 1/32 second accuracy |
| 57 struct epoch_ticks | |
| 58 { | |
| 59 uint32_t ticks; | |
| 60 // remainder | |
| 61 uint8_t rem; | |
| 62 }; | |
| 63 | |
|
15
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
64 // OCR1A ticks COUNTER_DIV(=4) times a second, we divide it down. |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
65 static uint8_t counter_div = 0; |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
66 |
| 16 | 67 #define WATCHDOG_LONG_MIN (60L*40) // 40 mins |
| 68 #define WATCHDOG_LONG_MAX (60L*60*72) // 72 hours | |
| 69 #define WATCHDOG_LONG_DEFAULT (60L*60*6) // 6 hours | |
| 70 | |
| 71 #define WATCHDOG_SHORT_MIN (60L*15) // 15 mins | |
| 72 | |
| 73 #define NEWBOOT_DEFAULT (60*10) // 10 minutes | |
| 74 #define NEWBOOT_MIN (60*2) // 2 minutes | |
| 75 #define NEWBOOT_MAX (60*30) // 30 mins | |
| 76 | |
| 1 | 77 // eeprom-settable parameters, default values defined here. |
| 78 // all timeouts should be a multiple of TICK | |
| 16 | 79 static uint32_t watchdog_long_limit = WATCHDOG_LONG_DEFAULT; |
| 1 | 80 static uint32_t watchdog_short_limit = 0; |
| 16 | 81 static uint32_t newboot_limit = NEWBOOT_DEFAULT; |
| 0 | 82 |
| 1 | 83 // avr proves itself |
| 2 | 84 static uint8_t avr_keys[NKEYS][KEYLEN] = {{0}}; |
| 0 | 85 |
| 86 // ---- Atomic guards required accessing these variables | |
| 87 // clock_epoch in seconds | |
| 88 static uint32_t clock_epoch; | |
| 1 | 89 // watchdog counts up |
| 90 static uint32_t watchdog_long_count; | |
| 91 static uint32_t watchdog_short_count; | |
| 2 | 92 // newboot counts down |
| 1 | 93 static uint32_t newboot_count; |
| 2 | 94 // oneshot counts down |
| 95 static uint32_t oneshot_count; | |
| 96 | |
| 0 | 97 // ---- End atomic guards required |
| 98 | |
| 99 // boolean flags | |
| 1 | 100 static uint8_t watchdog_long_hit; |
| 101 static uint8_t watchdog_short_hit; | |
| 102 static uint8_t newboot_hit; | |
| 2 | 103 static uint8_t oneshot_hit; |
| 0 | 104 |
|
15
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
105 // flips between 0 and 1 each watchdog_long_hit, so eventually a |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
106 // working firmware should boot. set back to 0 for each 'alive' |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
107 // command |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
108 static uint8_t long_reboot_mode = 0; |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
109 |
| 0 | 110 static uint8_t readpos; |
| 1 | 111 static char readbuf[50]; |
| 0 | 112 static uint8_t have_cmd; |
| 113 | |
| 114 int uart_putchar(char c, FILE *stream); | |
| 115 static void long_delay(int ms); | |
| 116 static void blink(); | |
| 117 static uint16_t adc_vcc(); | |
| 2 | 118 static void set_pi_boot_normal(uint8_t normal); |
| 0 | 119 |
| 120 static FILE mystdout = FDEV_SETUP_STREAM(uart_putchar, NULL, | |
| 121 _FDEV_SETUP_WRITE); | |
| 122 | |
| 123 // thanks to http://projectgus.com/2010/07/eeprom-access-with-arduino/ | |
| 124 #define eeprom_read_to(dst_p, eeprom_field, dst_size) eeprom_read_block((dst_p), (void *)offsetof(struct __eeprom_data, eeprom_field), (dst_size)) | |
| 125 #define eeprom_read(dst, eeprom_field) eeprom_read_to((&dst), eeprom_field, sizeof(dst)) | |
| 126 #define eeprom_write_from(src_p, eeprom_field, src_size) eeprom_write_block((src_p), (void *)offsetof(struct __eeprom_data, eeprom_field), (src_size)) | |
| 127 #define eeprom_write(src, eeprom_field) { eeprom_write_from(&src, eeprom_field, sizeof(src)); } | |
| 128 | |
| 1 | 129 #define EXPECT_MAGIC 0xdf83 |
| 0 | 130 |
| 131 struct __attribute__ ((__packed__)) __eeprom_data { | |
| 1 | 132 uint32_t watchdog_long_limit; |
| 133 uint32_t watchdog_short_limit; | |
| 134 uint32_t newboot_limit; | |
| 0 | 135 |
| 2 | 136 uint8_t avr_keys[NKEYS][KEYLEN]; |
| 0 | 137 |
| 138 uint16_t magic; | |
| 139 }; | |
| 140 | |
| 141 // Very first setup | |
| 142 static void | |
| 143 setup_chip() | |
| 144 { | |
| 145 cli(); | |
| 146 | |
| 147 // stop watchdog timer (might have been used to cause a reset) | |
| 148 wdt_reset(); | |
| 149 MCUSR &= ~_BV(WDRF); | |
| 150 WDTCSR |= _BV(WDCE) | _BV(WDE); | |
| 151 WDTCSR = 0; | |
| 152 | |
|
15
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
153 // set to 8 seconds, in case sha1 is slow etc. |
| 1 | 154 wdt_enable(WDTO_8S); |
| 155 | |
|
15
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
156 // Set scaler to /1, -> clock to 8mhz |
| 0 | 157 CLKPR = _BV(CLKPCE); |
|
15
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
158 CLKPR = 0; |
| 0 | 159 |
| 160 // enable pullups | |
| 1 | 161 // XXX matt pihelp |
| 5 | 162 //PORTB = 0xff; // XXX change when using SPI |
| 163 //PORTD = 0xff; | |
| 164 //PORTC = 0xff; | |
| 0 | 165 |
| 166 // 3.3v power for bluetooth and SD | |
|
15
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
167 //DDR_LED |= _BV(PIN_LED); |
| 0 | 168 |
| 5 | 169 #if 0 |
| 0 | 170 // set pullup |
| 171 PORTD |= _BV(PD2); | |
| 172 // INT0 setup | |
| 173 EICRA = (1<<ISC01); // falling edge - data sheet says it won't work? | |
| 174 EIMSK = _BV(INT0); | |
| 5 | 175 #endif |
| 0 | 176 |
| 177 // comparator disable | |
| 178 ACSR = _BV(ACD); | |
| 179 | |
| 180 // disable adc pin input buffers | |
| 181 DIDR0 = 0x3F; // acd0-adc5 | |
| 182 DIDR1 = (1<<AIN1D)|(1<<AIN0D); // ain0/ain1 | |
| 183 | |
| 184 sei(); | |
| 185 } | |
| 186 | |
| 187 static void | |
| 188 get_epoch_ticks(struct epoch_ticks *t) | |
| 189 { | |
| 190 ATOMIC_BLOCK(ATOMIC_RESTORESTATE) | |
| 191 { | |
| 192 t->ticks = clock_epoch; | |
| 7 | 193 t->rem = TCNT1; |
| 0 | 194 } |
| 195 } | |
| 196 | |
| 197 static void | |
| 198 setup_tick_counter() | |
| 199 { | |
| 2 | 200 // set up counter1 |
| 201 | |
| 0 | 202 // set up counter2. |
| 203 // COM21 COM20 Set OC2 on Compare Match (p116) | |
| 204 // WGM21 Clear counter on compare | |
| 205 //TCCR2A = _BV(COM2A1) | _BV(COM2A0) | _BV(WGM21); | |
| 206 // toggle on match | |
| 2 | 207 TCCR1A = _BV(COM1A0); |
| 8 | 208 #ifdef SIM_DEBUG |
| 209 // systemclock/8 | |
| 210 TCCR1B = _BV(CS11); | |
| 211 #else | |
| 7 | 212 // systemclock/64 |
| 213 TCCR1B = _BV(CS11) | _BV(CS10); | |
| 8 | 214 #endif |
| 2 | 215 TCNT1 = 0; |
| 216 OCR1A = SLEEP_COMPARE; | |
| 0 | 217 // interrupt |
| 2 | 218 TIMSK1 = _BV(OCIE1A); |
| 0 | 219 } |
| 220 | |
| 221 static void | |
| 222 uart_on() | |
| 223 { | |
| 224 // Power reduction register | |
| 225 PRR &= ~_BV(PRUSART0); | |
| 226 | |
| 227 // All of this needs to be done each time after turning off the PRR | |
| 228 // baud rate | |
| 229 UBRR0H = (unsigned char)(UBRR >> 8); | |
| 230 UBRR0L = (unsigned char)UBRR; | |
| 231 // set 2x clock, improves accuracy of UBRR | |
| 232 UCSR0A |= _BV(U2X0); | |
| 233 UCSR0B = _BV(RXCIE0) | _BV(RXEN0) | _BV(TXEN0); | |
| 234 //8N1 | |
| 235 UCSR0C = _BV(UCSZ01) | _BV(UCSZ00); | |
| 236 } | |
| 237 | |
| 238 static void | |
| 239 uart_off() | |
| 240 { | |
| 241 // Turn off interrupts and disable tx/rx | |
| 242 UCSR0B = 0; | |
| 243 | |
| 244 // Power reduction register | |
| 245 PRR |= _BV(PRUSART0); | |
| 246 } | |
| 247 | |
| 248 int | |
| 249 uart_putchar(char c, FILE *stream) | |
| 250 { | |
| 251 // XXX could perhaps sleep in the loop for power. | |
| 252 if (c == '\n') | |
| 253 { | |
| 254 loop_until_bit_is_set(UCSR0A, UDRE0); | |
| 255 UDR0 = '\r'; | |
| 256 } | |
| 257 loop_until_bit_is_set(UCSR0A, UDRE0); | |
| 258 UDR0 = c; | |
| 259 if (c == '\r') | |
| 260 { | |
| 261 loop_until_bit_is_set(UCSR0A, UDRE0); | |
| 262 UDR0 = '\n'; | |
| 263 } | |
| 264 return (unsigned char)c; | |
| 265 } | |
| 266 | |
| 267 static void | |
| 268 cmd_reset() | |
| 269 { | |
| 270 printf_P(PSTR("reset\n")); | |
| 271 _delay_ms(100); | |
| 272 cli(); // disable interrupts | |
| 273 wdt_enable(WDTO_15MS); // enable watchdog | |
| 274 while(1); // wait for watchdog to reset processor | |
| 275 } | |
| 276 | |
| 2 | 277 static void |
| 278 cmd_newboot() | |
| 279 { | |
| 280 set_pi_boot_normal(1); | |
| 281 ATOMIC_BLOCK(ATOMIC_RESTORESTATE) | |
| 282 { | |
| 283 newboot_count = newboot_limit; | |
| 284 } | |
| 285 printf_P(PSTR("newboot for %d secs"), newboot_limit); | |
| 286 } | |
| 287 | |
|
15
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
288 static void |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
289 cmd_oldboot() |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
290 { |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
291 set_pi_boot_normal(0); |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
292 ATOMIC_BLOCK(ATOMIC_RESTORESTATE) |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
293 { |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
294 newboot_count = 0; |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
295 } |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
296 printf_P(PSTR("back to old boot\n")); |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
297 } |
| 1 | 298 |
| 0 | 299 |
| 300 static void | |
| 1 | 301 cmd_get_params() |
| 0 | 302 { |
| 2 | 303 uint32_t cur_watchdog_long, cur_watchdog_short, cur_newboot, cur_oneshot; |
| 1 | 304 ATOMIC_BLOCK(ATOMIC_RESTORESTATE) |
| 305 { | |
| 2 | 306 cur_watchdog_long = watchdog_long_count; |
| 307 cur_watchdog_short = watchdog_short_count; | |
| 308 cur_newboot = newboot_count; | |
| 309 cur_oneshot = oneshot_count; | |
| 1 | 310 } |
| 311 | |
| 2 | 312 printf_P(PSTR("limit (count) : watchdog_long %lu (%lu) watchdog_short %lu (%lu) newboot %lu (%lu) oneshot (%lu)\n"), |
| 1 | 313 watchdog_long_limit, |
| 2 | 314 cur_watchdog_long, |
| 1 | 315 watchdog_short_limit, |
| 2 | 316 cur_watchdog_short, |
| 1 | 317 newboot_limit, |
| 2 | 318 cur_newboot, |
| 319 cur_oneshot); | |
| 0 | 320 } |
| 321 | |
| 322 static void | |
| 1 | 323 cmd_set_params(const char *params) |
| 0 | 324 { |
| 1 | 325 uint32_t new_watchdog_long_limit; |
| 326 uint32_t new_watchdog_short_limit; | |
| 327 uint32_t new_newboot_limit; | |
| 328 | |
| 329 int ret = sscanf_P(params, PSTR("%lu %lu %lu"), | |
| 330 &new_watchdog_long_limit, | |
| 331 &new_watchdog_short_limit, | |
| 332 &new_newboot_limit); | |
| 333 | |
| 334 | |
| 335 if (ret != 3) | |
| 0 | 336 { |
| 1 | 337 printf_P(PSTR("Bad values\n")); |
| 338 } | |
| 339 else | |
| 340 { | |
| 341 ATOMIC_BLOCK(ATOMIC_RESTORESTATE) | |
| 342 { | |
| 343 eeprom_write(new_watchdog_long_limit, watchdog_long_limit); | |
| 344 eeprom_write(new_watchdog_short_limit, watchdog_short_limit); | |
| 345 eeprom_write(new_newboot_limit, newboot_limit); | |
| 346 uint16_t magic = EXPECT_MAGIC; | |
| 347 eeprom_write(magic, magic); | |
| 0 | 348 } |
| 1 | 349 printf_P(PSTR("set_params for next boot\n")); |
| 350 printf_P(PSTR("watchdog_long %lu watchdog_short %lu newboot %lu\n"), | |
| 351 new_watchdog_long_limit, | |
| 352 new_watchdog_short_limit, | |
| 353 new_newboot_limit); | |
| 354 | |
| 355 } | |
| 356 } | |
| 0 | 357 |
| 1 | 358 uint8_t from_hex(char c) |
| 359 { | |
| 360 if (c >= '0' && c <= '9') { | |
| 361 return c-'0'; | |
| 362 } | |
| 363 if (c >= 'a' && c <= 'f') { | |
| 364 return c-'a' + 0xa; | |
| 365 } | |
| 366 if (c >= 'A' && c <= 'F') { | |
| 367 return c-'A' + 0xa; | |
| 368 } | |
| 369 return 0; | |
| 370 } | |
| 371 | |
| 2 | 372 static void |
| 373 printhex_nibble(const unsigned char b, FILE *stream) | |
| 374 { | |
| 375 unsigned char c = b & 0x0f; | |
| 376 if ( c > 9 ) { | |
| 377 c += 'A'-10; | |
| 378 } | |
| 379 else { | |
| 380 c += '0'; | |
| 381 } | |
| 382 fputc(c, stream); | |
| 383 } | |
| 384 | |
| 385 void | |
| 386 printhex_byte(const unsigned char b, FILE *stream) | |
| 387 { | |
| 388 printhex_nibble( b >> 4, stream); | |
| 389 printhex_nibble( b, stream); | |
| 390 } | |
| 391 | |
| 392 void | |
| 393 printhex(uint8_t *id, uint8_t n, FILE *stream) | |
| 394 { | |
| 395 for (uint8_t i = 0; i < n; i++) | |
| 396 { | |
| 397 if (i > 0) | |
| 398 { | |
| 399 fputc(' ', stream); | |
| 400 } | |
| 401 printhex_byte(id[i], stream); | |
| 402 } | |
| 403 } | |
| 404 | |
| 405 static int8_t | |
| 5 | 406 parse_key(const char *params, uint8_t *key_index, uint8_t *bytes, |
| 407 uint8_t bytes_len) | |
| 2 | 408 { |
| 409 // "N HEXKEY" | |
| 5 | 410 if (strlen(params) != bytes_len*2 + 2) { |
| 2 | 411 printf_P(PSTR("Wrong length key\n")); |
| 412 return -1; | |
| 413 } | |
| 414 | |
| 415 if (params[1] != ' ') | |
| 416 { | |
| 417 printf_P(PSTR("Missing space\n")); | |
| 418 return -1; | |
| 419 } | |
| 420 | |
| 421 *key_index = from_hex(params[0]); | |
| 422 if (*key_index >= NKEYS) | |
| 423 { | |
| 424 printf_P(PSTR("Bad key index %d, max %d\n"), *key_index, NKEYS); | |
| 425 return -1; | |
| 426 } | |
| 427 | |
| 5 | 428 for (int i = 0, p = 0; i < bytes_len; i++, p += 2) |
| 2 | 429 { |
| 430 bytes[i] = (from_hex(params[p+2]) << 4) | from_hex(params[p+3]); | |
| 431 } | |
| 432 return 0; | |
| 433 } | |
| 434 | |
| 1 | 435 static void |
| 436 cmd_set_avr_key(const char *params) | |
| 437 { | |
| 2 | 438 uint8_t new_key[KEYLEN]; |
| 439 uint8_t key_index; | |
| 5 | 440 if (parse_key(params, &key_index, new_key, sizeof(new_key)) != 0) |
| 2 | 441 { |
| 1 | 442 return; |
| 0 | 443 } |
| 2 | 444 memcpy(avr_keys[key_index], new_key, sizeof(new_key)); |
| 8 | 445 #ifndef SIM_DEBUG |
| 2 | 446 eeprom_write(avr_keys, avr_keys); |
| 8 | 447 #endif |
| 2 | 448 } |
| 449 | |
| 450 static void | |
| 451 cmd_hmac(const char *params) | |
| 452 { | |
|
11
e83b35e864d7
hmac and decrypt keys differ now
Matt Johnston <matt@ucc.asn.au>
parents:
8
diff
changeset
|
453 uint8_t indata[2+HMACLEN] = {'H', ':'}; |
| 7 | 454 uint8_t outdata[HMACLEN]; |
| 2 | 455 uint8_t key_index; |
|
11
e83b35e864d7
hmac and decrypt keys differ now
Matt Johnston <matt@ucc.asn.au>
parents:
8
diff
changeset
|
456 if (parse_key(params, &key_index, &indata[2], HMACLEN) != 0) |
| 2 | 457 { |
| 458 printf_P(PSTR("FAIL: Bad input\n")); | |
| 5 | 459 return; |
| 2 | 460 } |
| 0 | 461 |
| 8 | 462 #ifndef SIM_DEBUG |
| 5 | 463 long_delay(200); |
| 8 | 464 #endif |
| 5 | 465 |
|
11
e83b35e864d7
hmac and decrypt keys differ now
Matt Johnston <matt@ucc.asn.au>
parents:
8
diff
changeset
|
466 hmac_sha1(outdata, avr_keys[key_index], KEYLEN*8, indata, sizeof(indata)*8); |
| 2 | 467 printf_P(PSTR("HMAC: ")); |
| 7 | 468 printhex(outdata, HMACLEN, stdout); |
| 5 | 469 fputc('\n', stdout); |
| 470 } | |
| 471 | |
| 472 static void | |
| 473 cmd_decrypt(const char *params) | |
| 474 { | |
|
11
e83b35e864d7
hmac and decrypt keys differ now
Matt Johnston <matt@ucc.asn.au>
parents:
8
diff
changeset
|
475 uint8_t indata[HMACLEN+AESLEN]; // XXX |
|
e83b35e864d7
hmac and decrypt keys differ now
Matt Johnston <matt@ucc.asn.au>
parents:
8
diff
changeset
|
476 // a temporary buffer |
|
e83b35e864d7
hmac and decrypt keys differ now
Matt Johnston <matt@ucc.asn.au>
parents:
8
diff
changeset
|
477 uint8_t output[HMACLEN] = {'D', ':'}; |
|
e83b35e864d7
hmac and decrypt keys differ now
Matt Johnston <matt@ucc.asn.au>
parents:
8
diff
changeset
|
478 _Static_assert(AESLEN+2 <= sizeof(output), "sufficient output buffer"); |
| 5 | 479 uint8_t key_index; |
|
11
e83b35e864d7
hmac and decrypt keys differ now
Matt Johnston <matt@ucc.asn.au>
parents:
8
diff
changeset
|
480 if (parse_key(params, &key_index, indata, sizeof(indata)) != 0) |
| 5 | 481 { |
| 482 printf_P(PSTR("FAIL: Bad input\n")); | |
| 483 return; | |
| 484 } | |
| 485 | |
| 8 | 486 #ifndef SIM_DEBUG |
| 5 | 487 long_delay(200); |
| 8 | 488 #endif |
| 7 | 489 |
| 5 | 490 // check the signature |
|
11
e83b35e864d7
hmac and decrypt keys differ now
Matt Johnston <matt@ucc.asn.au>
parents:
8
diff
changeset
|
491 memcpy(&output[2], &indata[HMACLEN], AESLEN); |
| 12 | 492 hmac_sha1(output, avr_keys[key_index], KEYLEN*8, output, (2+AESLEN)*8); |
| 5 | 493 |
|
11
e83b35e864d7
hmac and decrypt keys differ now
Matt Johnston <matt@ucc.asn.au>
parents:
8
diff
changeset
|
494 if (memcmp(output, indata, HMACLEN) != 0) { |
| 5 | 495 printf_P(PSTR("FAIL: hmac mismatch\n")); |
| 496 } | |
| 497 | |
|
11
e83b35e864d7
hmac and decrypt keys differ now
Matt Johnston <matt@ucc.asn.au>
parents:
8
diff
changeset
|
498 uint8_t tmpbuf[256]; |
|
e83b35e864d7
hmac and decrypt keys differ now
Matt Johnston <matt@ucc.asn.au>
parents:
8
diff
changeset
|
499 aesInit(avr_keys[key_index], tmpbuf); |
|
e83b35e864d7
hmac and decrypt keys differ now
Matt Johnston <matt@ucc.asn.au>
parents:
8
diff
changeset
|
500 aesDecrypt(&indata[HMACLEN], NULL); |
| 5 | 501 |
| 502 printf_P(PSTR("DECRYPTED: ")); | |
| 503 printhex(output, AESLEN, stdout); | |
| 2 | 504 fputc('\n', stdout); |
| 505 } | |
| 506 | |
| 507 static void | |
| 508 cmd_oneshot_reboot(const char *params) | |
| 509 { | |
| 510 uint32_t new_delay = strtoul(params, NULL, 10); | |
| 511 ATOMIC_BLOCK(ATOMIC_RESTORESTATE) | |
| 1 | 512 { |
| 2 | 513 oneshot_count = new_delay; |
| 1 | 514 } |
|
15
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
515 printf_P(PSTR("oneshot new delay %lu\n"), new_delay); |
| 0 | 516 } |
| 517 | |
| 518 static void | |
| 519 load_params() | |
| 520 { | |
| 521 uint16_t magic; | |
| 522 eeprom_read(magic, magic); | |
| 523 if (magic == EXPECT_MAGIC) | |
| 524 { | |
| 1 | 525 eeprom_read(watchdog_long_limit, watchdog_long_limit); |
| 526 eeprom_read(watchdog_short_limit, watchdog_short_limit); | |
| 2 | 527 eeprom_read(newboot_limit, newboot_limit); |
| 1 | 528 } |
| 2 | 529 |
| 16 | 530 if (watchdog_long_limit < WATCHDOG_LONG_MIN |
| 531 || watchdog_long_limit > WATCHDOG_LONG_MAX) | |
| 532 { | |
| 533 watchdog_long_limit = WATCHDOG_LONG_DEFAULT; | |
| 534 } | |
| 535 | |
| 536 if (watchdog_short_limit != 0 | |
| 537 && watchdog_short_limit < WATCHDOG_SHORT_MIN) | |
| 538 { | |
| 539 watchdog_short_limit = 0; | |
| 540 } | |
| 541 | |
| 542 if (newboot_limit < NEWBOOT_MIN || newboot_limit > NEWBOOT_MAX) | |
| 543 { | |
| 544 newboot_limit = NEWBOOT_DEFAULT; | |
| 545 } | |
| 546 | |
| 547 _Static_assert(NEWBOOT_MAX < WATCHDOG_LONG_MIN, "newboot max shorter than watchdog min"); | |
| 548 | |
| 2 | 549 eeprom_read(avr_keys, avr_keys); |
| 0 | 550 } |
| 551 | |
| 2 | 552 static void |
|
15
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
553 cmd_alive() |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
554 { |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
555 printf_P(PSTR("Ah, good.\n")); |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
556 ATOMIC_BLOCK(ATOMIC_RESTORESTATE) |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
557 { |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
558 watchdog_long_count = 0; |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
559 watchdog_short_count = 0; |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
560 } |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
561 long_reboot_mode = 0; |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
562 } |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
563 |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
564 static void |
| 2 | 565 cmd_vcc() |
| 0 | 566 { |
| 2 | 567 uint16_t vcc = adc_vcc(); |
| 12 | 568 printf_P(PSTR("vcc: %u mV\n"), vcc); |
| 0 | 569 } |
| 570 | |
| 571 static void | |
| 572 read_handler() | |
| 573 { | |
|
15
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
574 // TODO: make this an array, print automatic help |
| 2 | 575 if (strcmp_P(readbuf, PSTR("get_params")) == 0) |
| 0 | 576 { |
| 577 cmd_get_params(); | |
| 578 } | |
| 579 else if (strncmp_P(readbuf, PSTR("set_params "), 11) == 0) | |
| 580 { | |
| 581 cmd_set_params(&readbuf[11]); | |
| 582 } | |
| 2 | 583 else if (strncmp_P(readbuf, PSTR("set_key "), 8) == 0) |
| 0 | 584 { |
| 2 | 585 cmd_set_avr_key(&readbuf[8]); |
| 0 | 586 } |
| 2 | 587 else if (strncmp_P(readbuf, PSTR("oneshot "), 8) == 0) |
| 0 | 588 { |
| 2 | 589 cmd_oneshot_reboot(&readbuf[8]); |
| 0 | 590 } |
| 2 | 591 else if (strncmp_P(readbuf, PSTR("hmac "), 5) == 0) |
| 0 | 592 { |
| 2 | 593 cmd_hmac(&readbuf[5]); |
| 0 | 594 } |
| 5 | 595 else if (strncmp_P(readbuf, PSTR("decrypt "), 8) == 0) |
| 596 { | |
| 12 | 597 cmd_decrypt(&readbuf[8]); |
| 5 | 598 } |
|
15
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
599 else if (strcmp_P(readbuf, PSTR("alive")) == 0) |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
600 { |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
601 cmd_alive(); |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
602 } |
| 2 | 603 else if (strcmp_P(readbuf, PSTR("vcc")) == 0) |
| 0 | 604 { |
| 2 | 605 cmd_vcc(); |
| 0 | 606 } |
| 607 else if (strcmp_P(readbuf, PSTR("reset")) == 0) | |
| 608 { | |
| 609 cmd_reset(); | |
| 610 } | |
| 4 | 611 else if (strcmp_P(readbuf, PSTR("newboot")) == 0) |
| 612 { | |
| 613 cmd_newboot(); | |
| 614 } | |
|
15
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
615 else if (strcmp_P(readbuf, PSTR("oldboot")) == 0) |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
616 { |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
617 cmd_oldboot(); |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
618 } |
| 0 | 619 else |
| 620 { | |
| 621 printf_P(PSTR("Bad command '%s'\n"), readbuf); | |
| 622 } | |
| 623 } | |
| 624 | |
| 625 ISR(INT0_vect) | |
| 626 { | |
| 627 blink(); | |
| 628 _delay_ms(100); | |
| 629 blink(); | |
| 630 } | |
| 631 | |
| 632 ISR(USART_RX_vect) | |
| 633 { | |
| 634 char c = UDR0; | |
| 635 #ifdef HAVE_UART_ECHO | |
| 636 uart_putchar(c, NULL); | |
| 637 #endif | |
| 638 if (c == '\r' || c == '\n') | |
| 639 { | |
| 640 if (readpos > 0) | |
| 641 { | |
| 642 readbuf[readpos] = '\0'; | |
| 643 have_cmd = 1; | |
| 644 readpos = 0; | |
| 645 } | |
| 646 } | |
| 647 else | |
| 648 { | |
| 649 readbuf[readpos] = c; | |
| 650 readpos++; | |
| 651 if (readpos >= sizeof(readbuf)) | |
| 652 { | |
| 653 readpos = 0; | |
| 654 } | |
| 655 } | |
| 656 } | |
| 657 | |
| 2 | 658 ISR(TIMER1_COMPA_vect) |
| 0 | 659 { |
| 2 | 660 TCNT1 = 0; |
|
15
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
661 counter_div++; |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
662 if (counter_div < COUNTER_DIV) |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
663 { |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
664 return; |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
665 } |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
666 counter_div = 0; |
| 0 | 667 |
| 668 clock_epoch += TICK; | |
| 669 | |
| 1 | 670 // watchdogs count up, continuous |
| 671 if (watchdog_long_limit > 0) { | |
| 2 | 672 watchdog_long_count += TICK; |
| 1 | 673 if (watchdog_long_count >= watchdog_long_limit) |
| 674 { | |
| 675 watchdog_long_count = 0; | |
| 676 watchdog_long_hit = 1; | |
| 677 } | |
| 0 | 678 } |
| 679 | |
| 1 | 680 if (watchdog_short_limit > 0) { |
| 2 | 681 watchdog_short_count += TICK; |
| 1 | 682 if (watchdog_short_count >= watchdog_short_limit) |
| 683 { | |
| 684 watchdog_short_count = 0; | |
| 685 watchdog_short_hit = 1; | |
| 686 } | |
| 0 | 687 } |
| 688 | |
| 2 | 689 // newboot counts down |
| 1 | 690 if (newboot_count > 0) |
| 0 | 691 { |
| 2 | 692 newboot_count-=TICK; |
| 693 if (newboot_count <= 0) | |
| 1 | 694 { |
| 695 newboot_hit = 1; | |
| 2 | 696 newboot_count = 0; |
| 1 | 697 } |
| 0 | 698 } |
| 1 | 699 |
| 2 | 700 if (oneshot_count > 0) |
| 701 { | |
| 702 oneshot_count-=TICK; | |
| 703 if (oneshot_count <= 0) | |
| 704 { | |
| 705 oneshot_hit = 1; | |
| 706 oneshot_count = 0; | |
| 707 } | |
| 708 } | |
| 0 | 709 } |
| 710 | |
| 711 static void | |
| 712 idle_sleep() | |
| 713 { | |
| 714 set_sleep_mode(SLEEP_MODE_IDLE); | |
| 715 sleep_mode(); | |
| 716 } | |
| 717 | |
| 718 static uint16_t | |
| 719 adc_vcc() | |
| 720 { | |
| 721 PRR &= ~_BV(PRADC); | |
| 722 | |
| 723 // /16 prescaler | |
| 724 ADCSRA = _BV(ADEN) | _BV(ADPS2); | |
| 725 | |
| 726 // set to measure 1.1 reference | |
| 727 ADMUX = _BV(REFS0) | _BV(MUX3) | _BV(MUX2) | _BV(MUX1); | |
| 728 // average a number of samples | |
| 729 uint16_t sum = 0; | |
| 730 uint8_t num = 0; | |
| 731 for (uint8_t n = 0; n < 20; n++) | |
| 732 { | |
| 733 ADCSRA |= _BV(ADSC); | |
| 734 loop_until_bit_is_clear(ADCSRA, ADSC); | |
| 735 | |
| 736 uint8_t low_11 = ADCL; | |
| 737 uint8_t high_11 = ADCH; | |
| 738 uint16_t val = low_11 + (high_11 << 8); | |
| 739 | |
| 740 if (n >= 4) | |
| 741 { | |
| 742 sum += val; | |
| 743 num++; | |
| 744 } | |
| 745 } | |
| 746 ADCSRA = 0; | |
| 747 PRR |= _BV(PRADC); | |
| 748 | |
| 749 //float res_volts = 1.1 * 1024 * num / sum; | |
| 750 //return 1000 * res_volts; | |
| 751 return ((uint32_t)1100*1024*num) / sum; | |
| 752 } | |
| 753 | |
| 754 static void | |
| 2 | 755 reboot_pi() |
| 756 { | |
| 757 // pull it low for 30ms | |
| 758 PORT_PI_RESET &= ~_BV(PIN_PI_RESET); | |
| 759 DDR_PI_RESET |= _BV(PIN_PI_RESET); | |
| 760 _delay_ms(30); | |
| 761 DDR_PI_RESET &= ~_BV(PIN_PI_RESET); | |
| 762 } | |
| 763 | |
| 764 static void | |
| 765 set_pi_boot_normal(uint8_t normal) | |
| 766 { | |
| 767 PORT_PI_BOOT &= ~_BV(PIN_PI_BOOT); | |
| 768 if (normal) | |
| 769 { | |
| 770 // tristate | |
| 771 DDR_PI_BOOT &= ~_BV(PIN_PI_BOOT); | |
| 772 } | |
| 773 else | |
| 774 { | |
| 775 // pull it low | |
| 776 DDR_PI_RESET |= _BV(PIN_PI_BOOT); | |
| 777 | |
| 778 } | |
| 779 } | |
| 780 | |
| 781 static void | |
| 782 check_flags() | |
| 783 { | |
|
15
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
784 if (watchdog_long_hit) |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
785 { |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
786 // alternate between booting normal and emergency |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
787 if (long_reboot_mode) |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
788 { |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
789 cmd_newboot(); |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
790 } |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
791 long_reboot_mode ^= 1; |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
792 } |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
793 |
| 2 | 794 if (watchdog_long_hit |
| 795 || watchdog_short_hit | |
| 796 || oneshot_hit) | |
| 797 { | |
| 12 | 798 printf_P(PSTR("Rebooting! long %d, short %d, oneshot %d\n"), |
| 799 watchdog_long_hit, watchdog_short_hit, oneshot_hit); | |
| 800 long_delay(300); | |
| 2 | 801 reboot_pi(); |
| 802 } | |
| 803 | |
| 804 if (newboot_hit) { | |
| 805 set_pi_boot_normal(0); | |
| 806 } | |
| 807 | |
| 808 watchdog_long_hit = 0; | |
| 809 watchdog_short_hit = 0; | |
| 810 newboot_hit = 0; | |
| 811 oneshot_hit = 0; | |
| 812 } | |
| 813 | |
| 814 static void | |
| 0 | 815 do_comms() |
| 816 { | |
| 817 // avoid receiving rubbish, perhaps | |
| 818 uart_on(); | |
| 819 | |
| 820 // write sd card here? same 3.3v regulator... | |
| 821 | |
| 1 | 822 while (1) |
| 0 | 823 { |
| 1 | 824 wdt_reset(); |
| 2 | 825 |
| 826 check_flags(); | |
| 827 | |
| 0 | 828 if (have_cmd) |
| 829 { | |
| 830 have_cmd = 0; | |
| 831 read_handler(); | |
| 832 continue; | |
| 833 } | |
| 834 | |
| 835 // wait for commands from the master | |
| 836 idle_sleep(); | |
| 837 } | |
| 838 } | |
| 839 | |
| 840 static void | |
| 841 blink() | |
| 842 { | |
| 843 PORT_LED &= ~_BV(PIN_LED); | |
| 844 _delay_ms(1); | |
| 845 PORT_LED |= _BV(PIN_LED); | |
| 846 } | |
| 847 | |
| 848 static void | |
| 849 long_delay(int ms) | |
| 850 { | |
| 851 int iter = ms / 100; | |
| 852 | |
| 853 for (int i = 0; i < iter; i++) | |
| 854 { | |
| 855 _delay_ms(100); | |
| 856 } | |
| 857 } | |
| 858 | |
| 859 ISR(BADISR_vect) | |
| 860 { | |
| 861 //uart_on(); | |
| 862 printf_P(PSTR("Bad interrupt\n")); | |
| 863 } | |
| 864 | |
| 865 int main(void) | |
| 866 { | |
|
15
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
867 _Static_assert(F_CPU % 2000000 == 0, "F_CPU is a multiple of 2mhz for counter division"); |
|
915be6f0ff13
fix for 8mhz, add flip/flop long watchdog
Matt Johnston <matt@ucc.asn.au>
parents:
12
diff
changeset
|
868 |
| 0 | 869 setup_chip(); |
| 870 blink(); | |
| 871 | |
| 872 stdout = &mystdout; | |
| 873 uart_on(); | |
| 874 | |
| 12 | 875 printf_P(PSTR("Pi Watchdog\nMatt Johnston [email protected]")); |
| 0 | 876 |
| 2 | 877 set_pi_boot_normal(0); |
| 878 | |
| 0 | 879 load_params(); |
| 880 | |
| 881 setup_tick_counter(); | |
| 882 | |
| 883 sei(); | |
| 884 | |
| 8 | 885 #if 0 |
| 886 // encryption test | |
| 887 cmd_set_avr_key("1 6161626263636464656566666767686800000000"); | |
| 888 cmd_set_avr_key("2 7979757569696f6f646465656666717164646969"); | |
| 12 | 889 //cmd_decrypt("1 ecd858ee07a8e16575723513d2d072a7565865e40ba302059bfc650d4491268448102119"); |
| 890 cmd_decrypt("1 5a587b50fd48688bbda1b510cf9a3fab6fd4737b" "0ba302059bfc650d4491268448102119"); | |
| 891 cmd_hmac("2 7979757569696f6f646465656666717164646969"); | |
| 8 | 892 #endif |
| 893 | |
| 1 | 894 // doesn't return |
| 895 do_comms(); | |
| 0 | 896 |
| 897 return 0; /* never reached */ | |
| 898 } |