templog: server/ts.py annotate

annotate server/ts.py @ 117:eecd2612a68e

stay on

author	Matt Johnston <matt@ucc.asn.au>
date	Fri, 05 Oct 2012 22:48:49 +0800
parents	9485da05bc11
children	81591bdfa92c

rev	line source
21 2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	1 #!/usr/bin/env python2.7
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	2
23 b5925cb4f264 Fix bugs in server code (try actually running it) Matt Johnston <matt@ucc.asn.au> parents: 22 diff changeset	3 # time that the bluetooth takes to get going?
96 b2d0887fb306 be quicker responding Matt Johnston <matt@ucc.asn.au> parents: 94 diff changeset	4 EXTRA_WAKEUP = -3
23 b5925cb4f264 Fix bugs in server code (try actually running it) Matt Johnston <matt@ucc.asn.au> parents: 22 diff changeset	5
24 44c5ab5ea879 - some fixes for server code Matt Johnston <matt@ucc.asn.au> parents: 23 diff changeset	6 FETCH_TRIES = 3
44c5ab5ea879 - some fixes for server code Matt Johnston <matt@ucc.asn.au> parents: 23 diff changeset	7
23 b5925cb4f264 Fix bugs in server code (try actually running it) Matt Johnston <matt@ucc.asn.au> parents: 22 diff changeset	8 # avoid turning off the bluetooth etc.
42 26c8ab2ba3f1 mostly works Matt Johnston <matt@ucc.asn.au> parents: 40 diff changeset	9 TESTING = False
22 885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	10
21 2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	11 import sys
27 dbbd503119ba Add some web server handling Matt Johnston <matt@ucc.asn.au> parents: 26 diff changeset	12 # for wrt
dbbd503119ba Add some web server handling Matt Johnston <matt@ucc.asn.au> parents: 26 diff changeset	13 sys.path.append('/root/python')
dbbd503119ba Add some web server handling Matt Johnston <matt@ucc.asn.au> parents: 26 diff changeset	14 import httplib
22 885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	15 import time
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	16 import traceback
28 e3e0ed7758f9 hmac Matt Johnston <matt@ucc.asn.au> parents: 27 diff changeset	17 import binascii
e3e0ed7758f9 hmac Matt Johnston <matt@ucc.asn.au> parents: 27 diff changeset	18 import hmac
34 79124d7d3f79 - import zlib Matt Johnston <matt@ucc.asn.au> parents: 32 diff changeset	19 import zlib
35 4bfa9b7b2e4b - fix mac/urllib to work Matt Johnston <matt@ucc.asn.au> parents: 34 diff changeset	20 import urllib
4bfa9b7b2e4b - fix mac/urllib to work Matt Johnston <matt@ucc.asn.au> parents: 34 diff changeset	21 import urllib2
89 51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	22 import logging
51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	23
51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	24 L = logging.info
51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	25 W = logging.warning
51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	26 E = logging.error
28 e3e0ed7758f9 hmac Matt Johnston <matt@ucc.asn.au> parents: 27 diff changeset	27
e3e0ed7758f9 hmac Matt Johnston <matt@ucc.asn.au> parents: 27 diff changeset	28 import config
22 885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	29
26 d3e5934fe55c - Move crc16 to utils and fix it Matt Johnston <matt@ucc.asn.au> parents: 25 diff changeset	30 from utils import monotonic_time, retry, readline, crc16
66 c5ad12670cae dup2 to devnull Matt Johnston <matt@ucc.asn.au> parents: 65 diff changeset	31 import utils
21 2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	32
89 51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	33 import bluetooth
21 2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	34
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	35 def get_socket(addr):
89 51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	36 s = bluetooth.BluetoothSocket( bluetooth.RFCOMM )
96 b2d0887fb306 be quicker responding Matt Johnston <matt@ucc.asn.au> parents: 94 diff changeset	37 L("connecting")
89 51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	38 s.connect((addr, 1))
91 231662c6690c handle new next_wake format Matt Johnston <matt@ucc.asn.au> parents: 89 diff changeset	39 s.setblocking(False)
96 b2d0887fb306 be quicker responding Matt Johnston <matt@ucc.asn.au> parents: 94 diff changeset	40 s.settimeout(1)
91 231662c6690c handle new next_wake format Matt Johnston <matt@ucc.asn.au> parents: 89 diff changeset	41
21 2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	42 return s
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	43
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	44
22 885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	45 @retry()
21 2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	46 def fetch(sock):
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	47 sock.send("fetch\n")
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	48
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	49 crc = 0
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	50
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	51 lines = []
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	52 l = readline(sock)
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	53 if l != 'START\n':
96 b2d0887fb306 be quicker responding Matt Johnston <matt@ucc.asn.au> parents: 94 diff changeset	54 W("Bad expected START line '%s'\n" % str(l).rstrip('\n'))
21 2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	55 return None
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	56 crc = crc16(l, crc)
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	57
24 44c5ab5ea879 - some fixes for server code Matt Johnston <matt@ucc.asn.au> parents: 23 diff changeset	58 while True:
21 2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	59 l = readline(sock)
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	60
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	61 crc = crc16(l, crc)
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	62
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	63 if l == 'END\n':
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	64 break
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	65
27 dbbd503119ba Add some web server handling Matt Johnston <matt@ucc.asn.au> parents: 26 diff changeset	66 lines.append(l.rstrip('\n'))
21 2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	67
89 51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	68 for d in lines:
51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	69 L("Received: %s" % d)
51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	70
21 2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	71 l = readline(sock)
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	72 recv_crc = None
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	73 try:
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	74 k, v = l.rstrip('\n').split('=')
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	75 if k == 'CRC':
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	76 recv_crc = int(v)
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	77 if recv_crc < 0 or recv_crc > 0xffff:
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	78 recv_crc = None
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	79 except ValueError:
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	80 pass
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	81
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	82 if recv_crc is None:
89 51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	83 W("Bad expected CRC line '%s'\n" % l.rstrip('\n'))
21 2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	84 return None
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	85
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	86 if recv_crc != crc:
89 51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	87 W("Bad CRC: calculated 0x%x vs received 0x%x\n" % (crc, recv_crc))
21 2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	88 return None
2029633912c2 untested simple server proxy code Matt Johnston <matt@ucc.asn.au> parents: diff changeset	89
27 dbbd503119ba Add some web server handling Matt Johnston <matt@ucc.asn.au> parents: 26 diff changeset	90 return lines
22 885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	91
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	92 @retry()
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	93 def turn_off(sock):
23 b5925cb4f264 Fix bugs in server code (try actually running it) Matt Johnston <matt@ucc.asn.au> parents: 22 diff changeset	94 if TESTING:
42 26c8ab2ba3f1 mostly works Matt Johnston <matt@ucc.asn.au> parents: 40 diff changeset	95 return 99
89 51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	96 L("Sending btoff")
22 885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	97 sock.send("btoff\n");
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	98 # read newline
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	99 l = readline(sock)
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	100 if not l:
89 51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	101 W("Bad response to btoff")
22 885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	102 return None
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	103
91 231662c6690c handle new next_wake format Matt Johnston <matt@ucc.asn.au> parents: 89 diff changeset	104 if not l.startswith('next_wake'):
89 51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	105 W("Bad response to btoff '%s'" % l)
42 26c8ab2ba3f1 mostly works Matt Johnston <matt@ucc.asn.au> parents: 40 diff changeset	106 return None
91 231662c6690c handle new next_wake format Matt Johnston <matt@ucc.asn.au> parents: 89 diff changeset	107 L("Next wake line %s" % l)
22 885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	108
91 231662c6690c handle new next_wake format Matt Johnston <matt@ucc.asn.au> parents: 89 diff changeset	109 toks = dict(v.split('=') for v in l.split(','))
231662c6690c handle new next_wake format Matt Johnston <matt@ucc.asn.au> parents: 89 diff changeset	110
92 c3eb67cd8b61 handle rem from btoff Matt Johnston <matt@ucc.asn.au> parents: 91 diff changeset	111 rem = int(toks['rem'])
c3eb67cd8b61 handle rem from btoff Matt Johnston <matt@ucc.asn.au> parents: 91 diff changeset	112 tick_secs = int(toks['tick_secs'])
99 1a88bb989afb fix off-by-one in remainder code Matt Johnston <matt@ucc.asn.au> parents: 94 diff changeset	113 tick_wake = int(toks['tick_wake']) + 1
92 c3eb67cd8b61 handle rem from btoff Matt Johnston <matt@ucc.asn.au> parents: 91 diff changeset	114 next_wake = int(toks['next_wake'])
c3eb67cd8b61 handle rem from btoff Matt Johnston <matt@ucc.asn.au> parents: 91 diff changeset	115
c3eb67cd8b61 handle rem from btoff Matt Johnston <matt@ucc.asn.au> parents: 91 diff changeset	116 rem_secs = float(rem) / tick_wake * tick_secs
c3eb67cd8b61 handle rem from btoff Matt Johnston <matt@ucc.asn.au> parents: 91 diff changeset	117
c3eb67cd8b61 handle rem from btoff Matt Johnston <matt@ucc.asn.au> parents: 91 diff changeset	118 next_wake_secs = next_wake - rem_secs
c3eb67cd8b61 handle rem from btoff Matt Johnston <matt@ucc.asn.au> parents: 91 diff changeset	119 L("next_wake_secs %f\n", next_wake_secs)
c3eb67cd8b61 handle rem from btoff Matt Johnston <matt@ucc.asn.au> parents: 91 diff changeset	120 return next_wake_secs
22 885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	121
32 e18d7e89c17d More minor work Matt Johnston <matt@ucc.asn.au> parents: 29 diff changeset	122 @retry()
e18d7e89c17d More minor work Matt Johnston <matt@ucc.asn.au> parents: 29 diff changeset	123 def clear_meas(sock):
e18d7e89c17d More minor work Matt Johnston <matt@ucc.asn.au> parents: 29 diff changeset	124 sock.send("clear\n");
e18d7e89c17d More minor work Matt Johnston <matt@ucc.asn.au> parents: 29 diff changeset	125 l = readline(sock)
e18d7e89c17d More minor work Matt Johnston <matt@ucc.asn.au> parents: 29 diff changeset	126 if l and l.rstrip() == 'cleared':
e18d7e89c17d More minor work Matt Johnston <matt@ucc.asn.au> parents: 29 diff changeset	127 return True
e18d7e89c17d More minor work Matt Johnston <matt@ucc.asn.au> parents: 29 diff changeset	128
89 51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	129 E("Bad response to clear '%s'" % str(l))
32 e18d7e89c17d More minor work Matt Johnston <matt@ucc.asn.au> parents: 29 diff changeset	130 return False
e18d7e89c17d More minor work Matt Johnston <matt@ucc.asn.au> parents: 29 diff changeset	131
28 e3e0ed7758f9 hmac Matt Johnston <matt@ucc.asn.au> parents: 27 diff changeset	132 def send_results(lines):
29 048143905092 work on web interface Matt Johnston <matt@ucc.asn.au> parents: 28 diff changeset	133 enc_lines = binascii.b2a_base64(zlib.compress('\n'.join(lines)))
35 4bfa9b7b2e4b - fix mac/urllib to work Matt Johnston <matt@ucc.asn.au> parents: 34 diff changeset	134 mac = hmac.new(config.HMAC_KEY, enc_lines).hexdigest()
28 e3e0ed7758f9 hmac Matt Johnston <matt@ucc.asn.au> parents: 27 diff changeset	135
35 4bfa9b7b2e4b - fix mac/urllib to work Matt Johnston <matt@ucc.asn.au> parents: 34 diff changeset	136 url_data = urllib.urlencode( {'lines': enc_lines, 'hmac': mac} )
28 e3e0ed7758f9 hmac Matt Johnston <matt@ucc.asn.au> parents: 27 diff changeset	137 con = urllib2.urlopen(config.UPDATE_URL, url_data)
32 e18d7e89c17d More minor work Matt Johnston <matt@ucc.asn.au> parents: 29 diff changeset	138 result = con.read(100)
e18d7e89c17d More minor work Matt Johnston <matt@ucc.asn.au> parents: 29 diff changeset	139 if result == 'OK':
e18d7e89c17d More minor work Matt Johnston <matt@ucc.asn.au> parents: 29 diff changeset	140 return True
e18d7e89c17d More minor work Matt Johnston <matt@ucc.asn.au> parents: 29 diff changeset	141 else:
89 51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	142 W("Bad result '%s'" % result)
32 e18d7e89c17d More minor work Matt Johnston <matt@ucc.asn.au> parents: 29 diff changeset	143 return False
28 e3e0ed7758f9 hmac Matt Johnston <matt@ucc.asn.au> parents: 27 diff changeset	144
22 885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	145 def do_comms(sock):
89 51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	146 L("do_comms")
22 885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	147 d = None
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	148 # serial could be unreliable, try a few times
89 51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	149 d = fetch(sock)
22 885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	150 if not d:
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	151 return
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	152
27 dbbd503119ba Add some web server handling Matt Johnston <matt@ucc.asn.au> parents: 26 diff changeset	153 res = send_results(d)
22 885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	154 if not res:
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	155 return
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	156
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	157 clear_meas(sock)
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	158
117 eecd2612a68e stay on Matt Johnston <matt@ucc.asn.au> parents: 100 diff changeset	159 next_wake = 600
eecd2612a68e stay on Matt Johnston <matt@ucc.asn.au> parents: 100 diff changeset	160 #next_wake = turn_off(sock)
22 885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	161 sock.close()
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	162 return next_wake
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	163
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	164 testcount = 0
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	165
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	166 def sleep_for(secs):
23 b5925cb4f264 Fix bugs in server code (try actually running it) Matt Johnston <matt@ucc.asn.au> parents: 22 diff changeset	167 until = monotonic_time() + secs
22 885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	168 while True:
24 44c5ab5ea879 - some fixes for server code Matt Johnston <matt@ucc.asn.au> parents: 23 diff changeset	169 length = until - monotonic_time()
22 885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	170 if length <= 0:
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	171 return
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	172 time.sleep(length)
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	173
89 51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	174 def setup_logging():
51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	175 logging.basicConfig(format='%(asctime)s %(message)s',
91 231662c6690c handle new next_wake format Matt Johnston <matt@ucc.asn.au> parents: 89 diff changeset	176 datefmt='%m/%d/%Y %I:%M:%S %p',
231662c6690c handle new next_wake format Matt Johnston <matt@ucc.asn.au> parents: 89 diff changeset	177 level=logging.INFO)
89 51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	178
22 885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	179 def main():
89 51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	180 setup_logging()
51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	181
51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	182 L("Running templog rfcomm server")
22 885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	183
65 b09c164debf6 cheap_daemon() Matt Johnston <matt@ucc.asn.au> parents: 47 diff changeset	184 if '--daemon' in sys.argv:
b09c164debf6 cheap_daemon() Matt Johnston <matt@ucc.asn.au> parents: 47 diff changeset	185 utils.cheap_daemon()
b09c164debf6 cheap_daemon() Matt Johnston <matt@ucc.asn.au> parents: 47 diff changeset	186
96 b2d0887fb306 be quicker responding Matt Johnston <matt@ucc.asn.au> parents: 94 diff changeset	187 next_wake_time = 0
22 885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	188 while True:
23 b5925cb4f264 Fix bugs in server code (try actually running it) Matt Johnston <matt@ucc.asn.au> parents: 22 diff changeset	189 sock = None
b5925cb4f264 Fix bugs in server code (try actually running it) Matt Johnston <matt@ucc.asn.au> parents: 22 diff changeset	190 try:
82 0f7c005b3f87 move server config into config.py Matt Johnston <matt@ucc.asn.au> parents: 66 diff changeset	191 sock = get_socket(config.BTADDR)
23 b5925cb4f264 Fix bugs in server code (try actually running it) Matt Johnston <matt@ucc.asn.au> parents: 22 diff changeset	192 except Exception, e:
94 229b740a607f use the remainder of times Matt Johnston <matt@ucc.asn.au> parents: 92 diff changeset	193 #logging.exception("Error connecting")
89 51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	194 pass
22 885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	195 if sock:
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	196 try:
89 51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	197 avr_wake = do_comms(sock)
51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	198 next_wake_time = time.time() + avr_wake
22 885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	199 except Exception, e:
89 51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	200 logging.exception("Error in do_comms")
22 885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	201
96 b2d0887fb306 be quicker responding Matt Johnston <matt@ucc.asn.au> parents: 94 diff changeset	202 next_wake_interval = next_wake_time - time.time() + EXTRA_WAKEUP
89 51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	203 sleep_time = config.SLEEP_TIME
51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	204 if next_wake_interval > 0:
51d889ad39a3 main.c : add a delay before turning on uart Matt Johnston <matt@ucc.asn.au> parents: 82 diff changeset	205 sleep_time = min(next_wake_interval, sleep_time)
96 b2d0887fb306 be quicker responding Matt Johnston <matt@ucc.asn.au> parents: 94 diff changeset	206 if next_wake_interval < 0 and next_wake_interval > -30:
b2d0887fb306 be quicker responding Matt Johnston <matt@ucc.asn.au> parents: 94 diff changeset	207 L("not sleeping, next_wake_interval overdue %f" % next_wake_interval)
b2d0887fb306 be quicker responding Matt Johnston <matt@ucc.asn.au> parents: 94 diff changeset	208 continue
b2d0887fb306 be quicker responding Matt Johnston <matt@ucc.asn.au> parents: 94 diff changeset	209 L("Sleeping for %d, next wake interval %f" % (sleep_time, next_wake_interval))
22 885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	210 sleep_for(sleep_time)
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	211
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	212 if __name__ == '__main__':
885532437100 A bit of work on the server python Matt Johnston <matt@ucc.asn.au> parents: 21 diff changeset	213 main()

Mercurial > templog

annotate server/ts.py @ 117:eecd2612a68e